Commit e0a1d139 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-spear', 'clk-fract', 'clk-rockchip' and 'clk-imx' into clk-next 

 - Debugfs support for fractional divider clk

* clk-spear:
  clk: spear: Fix SSP clock definition on SPEAr600
  clk: spear: Fix CLCD clock definition on SPEAr600

* clk-fract:
  clk: fractional-divider: Regroup inclusions
  clk: fractional-divider: Show numerator and denominator in debugfs
  clk: fractional-divider: Split out clk_fd_get_div() helper

* clk-rockchip:
  clk: rockchip: Fix memory leak in rockchip_clk_register_pll()
  clk: rockchip: add clock controller for the RK3588
  clk: rockchip: add lookup table support
  clk: rockchip: simplify rockchip_clk_add_lookup
  clk: rockchip: allow additional mux options for cpu-clock frequency changes
  clk: rockchip: add pll type for RK3588
  clk: rockchip: add register offset of the cores select parent
  dt-bindings: clock: add rk3588 cru bindings
  dt-bindings: reset: add rk3588 reset definitions
  dt-bindings: clock: add rk3588 clock definitions
  clk: rockchip: use proper crypto0 name on rk3399

* clk-imx:
  clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()
  clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
  clk: imx8mn: fix imx8mn_sai2_sels clocks list
  clk: imx: rename video_pll1 to video_pll
  clk: imx: replace osc_hdmi with dummy
  clk: imx8mn: rename vpu_pll to m7_alt_pll
  clk: imx: imxrt1050: add IMXRT1050_CLK_LCDIF_PIX clock gate
  clk: imx: imxrt1050: fix IMXRT1050_CLK_LCDIF_APB offsets
  clk: imx8mp: Add audio shared gate
  dt-bindings: clock: imx8mp: Add ids for the audio shared gate
  clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x
  clk: imx93: keep sys ctr clock always on
  clk: imx: keep hsio bus clock always on
  clk: imx93: drop tpm1/3, lpit1/2 clk
  dt-bindings: clock: imx93: drop TPM1/3 LPIT1/2 entry
  clk: imx93: correct enet clock
  clk: imx93: unmap anatop base in error handling path
  clk: imx: imx8mp: add shared clk gate for usb suspend clk
  dt-bindings: clocks: imx8mp: Add ID for usb suspend clock
  clk: imx93: correct the flexspi1 clock setting
parents 83907bf3 5381dc78 76c340e9 266162b7 5595eabd

Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml

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+71 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip rk3588 Family Clock and Reset Control Module



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The RK3588 clock controller generates the clock and also implements a reset

  controller for SoC peripherals. For example it provides SCLK_UART2 and

  PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART

  module.

  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All available clock and reset IDs

  are defined as preprocessor macros in dt-binding headers.



properties:

  compatible:

    enum:

      - rockchip,rk3588-cru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    minItems: 2

    maxItems: 2



  clock-names:

    items:

      - const: xin24m

      - const: xin32k



  assigned-clocks: true



  assigned-clock-rates: true



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: >

      phandle to the syscon managing the "general register files". It is used

      for GRF muxes, if missing any muxes present in the GRF will not be

      available.



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    cru: clock-controller@fd7c0000 {

      compatible = "rockchip,rk3588-cru";

      reg = <0xfd7c0000 0x5c000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

drivers/clk/clk-fractional-divider.c

+56 −9
Original line number Diff line number Diff line
@@ -38,12 +38,15 @@ 
 * saturated values.

 */



#include <linux/clk-provider.h>

#include <linux/debugfs.h>

#include <linux/device.h>

#include <linux/io.h>

#include <linux/math.h>

#include <linux/module.h>

#include <linux/device.h>

#include <linux/slab.h>

#include <linux/rational.h>

#include <linux/slab.h>



#include <linux/clk-provider.h>



#include "clk-fractional-divider.h"
@@ -63,14 +66,12 @@ static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val) 
		writel(val, fd->reg);

}



static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,

					unsigned long parent_rate)

static void clk_fd_get_div(struct clk_hw *hw, struct u32_fract *fract)

{

	struct clk_fractional_divider *fd = to_clk_fd(hw);

	unsigned long flags = 0;

	unsigned long m, n;

	u32 val;

	u64 ret;



	if (fd->lock)

		spin_lock_irqsave(fd->lock, flags);
@@ -92,11 +93,22 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, 
		n++;

	}



	if (!n || !m)

	fract->numerator = m;

	fract->denominator = n;

}



static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

	struct u32_fract fract;

	u64 ret;



	clk_fd_get_div(hw, &fract);



	if (!fract.numerator || !fract.denominator)

		return parent_rate;



	ret = (u64)parent_rate * m;

	do_div(ret, n);

	ret = (u64)parent_rate * fract.numerator;

	do_div(ret, fract.denominator);



	return ret;

}
@@ -183,10 +195,45 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



#ifdef CONFIG_DEBUG_FS

static int clk_fd_numerator_get(void *hw, u64 *val)

{

	struct u32_fract fract;



	clk_fd_get_div(hw, &fract);



	*val = fract.numerator;



	return 0;

}

DEFINE_DEBUGFS_ATTRIBUTE(clk_fd_numerator_fops, clk_fd_numerator_get, NULL, "%llu\n");



static int clk_fd_denominator_get(void *hw, u64 *val)

{

	struct u32_fract fract;



	clk_fd_get_div(hw, &fract);



	*val = fract.denominator;



	return 0;

}

DEFINE_DEBUGFS_ATTRIBUTE(clk_fd_denominator_fops, clk_fd_denominator_get, NULL, "%llu\n");



static void clk_fd_debug_init(struct clk_hw *hw, struct dentry *dentry)

{

	debugfs_create_file("numerator", 0444, dentry, hw, &clk_fd_numerator_fops);

	debugfs_create_file("denominator", 0444, dentry, hw, &clk_fd_denominator_fops);

}

#endif



const struct clk_ops clk_fractional_divider_ops = {

	.recalc_rate = clk_fd_recalc_rate,

	.round_rate = clk_fd_round_rate,

	.set_rate = clk_fd_set_rate,

#ifdef CONFIG_DEBUG_FS

	.debug_init = clk_fd_debug_init,

#endif

};

EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);

drivers/clk/imx/clk-imx6sll.c

+4 −4
Original line number Diff line number Diff line
@@ -91,12 +91,12 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) 


	hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);



	hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");

	hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");

	hws[IMX6SLL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");

	hws[IMX6SLL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");



	/* ipp_di clock is external input */

	hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");

	hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");

	hws[IMX6SLL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");

	hws[IMX6SLL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");



	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");

	base = of_iomap(np, 0);

drivers/clk/imx/clk-imx6sx.c

+6 −6
Original line number Diff line number Diff line
@@ -132,16 +132,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 


	hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);



	hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");

	hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");

	hws[IMX6SX_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");

	hws[IMX6SX_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");



	/* ipp_di clock is external input */

	hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");

	hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");

	hws[IMX6SX_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");

	hws[IMX6SX_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");



	/* Clock source from external clock via CLK1/2 PAD */

	hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1");

	hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2");

	hws[IMX6SX_CLK_ANACLK1] = imx_get_clk_hw_by_name(ccm_node, "anaclk1");

	hws[IMX6SX_CLK_ANACLK2] = imx_get_clk_hw_by_name(ccm_node, "anaclk2");



	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");

	base = of_iomap(np, 0);

drivers/clk/imx/clk-imx6ul.c

+4 −4
Original line number Diff line number Diff line
@@ -126,12 +126,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 


	hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);



	hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");

	hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");

	hws[IMX6UL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");

	hws[IMX6UL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");



	/* ipp_di clock is external input */

	hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");

	hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");

	hws[IMX6UL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");

	hws[IMX6UL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");



	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");

	base = of_iomap(np, 0);