- Nov 12, 2014
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Enric Balletbo i Serra authored
At this moment all supported boards use same NAND chip, so has more sense move the GPMC and NAND configuration to the omap3-igep.dtsi common place. Signed-off-by:
Enric Balletbo i Serra <eballetbo@iseebcn.com> Acked-by:
Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
UART2 is used to connect the processor with the bluetooth chip, these pins are not common between IGEPv2 boards and IGEP COM MODULE boards. This patch muxes the correct pins for every board and removes UART2 configuration from common omap3-igep.dtsi file. Signed-off-by:
Enric Balletbo i Serra <eballetbo@iseebcn.com> Acked-by:
Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Nov 11, 2014
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Felipe Balbi authored
by adding labels to DWC3 nodes, it's far easier for boards to reference them. Signed-off-by:
Felipe Balbi <balbi@ti.com> [tony@atomide.com: updated for otg 4 move to dra74x.dtsi] Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Mugunthan V N authored
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and sleep states and enable them in board evm dts file. Signed-off-by:
Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Nishanth Menon authored
DRA7 Data Manual (SPRS857L - August 2014) section 4.1.1 states: "All unused power supply balls must be supplied with the voltages specified in the Section 5.2, Recommended Operating Conditions". This implies that all unused voltage rails for Vayu can never be switched off even if the hardware blocks inside that voltage domain is unused. Switching off these unused rails may result in stability issues on other domains and increased leakage and power-on-hour impacts. J6eco-evm dts file already considers this, however j6evm-dts file needs to be fixed to consider this constraint of the SoC. Signed-off-by:
Nishanth Menon <nm@ti.com> Acked-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Nishanth Menon authored
Add MMC1 and 2 nodes. MMC1 is SDcard and MMC2 is eMMC. NOTE on MMC1 card detect: Ideally, we should be using in-built SDCD support, but we dont have it yet. So, use the fact that control module of DRA7 is setup such that no matter what mode one configures it, GPIO option is always hardwired in - use GPIO mode for SDcard detection. [peter.ujfalusi@ti.com] The power line feeding the SD card is also used by other devices on the EVM. Use generic name instead of mmc2_3v3 so when other devices want to use the same regulator it will look a bit better. Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Nishanth Menon authored
With Commit adff5962 ("Input: introduce palmas-pwrbutton"), we can now support tps power button as a event source - This is SW7 (PB/WAKE) on the J6-evm. Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Nishanth Menon authored
Even thought sys_nirq1 is hardwired on the SoC for the pin, it is better to configure the pin to the required mux configuration. Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
The ldo4_reg regulator provides power to the USB1 and USB2 High Speed PHYs. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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George Cherian authored
Add USB data and pinctrl for USB. Signed-off-by:
George Cherian <george.cherian@ti.com> Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
The 4th USB controller instance present only on the DRA74x family of devices so move it there. Signed-off-by:
Roger Quadros <rogerq@ti.com> Acked-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
DRA72-evm has a 256MB 16-bit wide NAND chip. Add pinmux and NAND node. The NAND chips 'Chip select' and 'Write protect' can be controlled using DIP Switch SW5. To use NAND, the switch must be configured like so: SW5.1 (NAND_SELn) = ON (LOW) SW5.9 (GPMC_WPN) = OFF (HIGH) Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Tested-by:
Nishanth Menon <nm@ti.com> Acked-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Mugunthan V N authored
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and sleep states and enable them in board evm dts file. Signed-off-by:
Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Mugunthan V N authored
Add CPSW and MDIO related device tree data for DRA7XX and made as status disabled. Phy-id, pinmux for active and sleep state needs to be added in board dts files and enable the CPSW device. Signed-off-by:
Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Marek Belisko authored
Use omap specific pinctrl defines (OMAP3_CORE1_IOPAD) to configure the padconf register offset. Signed-off-by:
Marek Belisko <marek@goldelico.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Dmitry Lifshitz authored
Add DSS related pinmux and display data nodes required to support DVI video out on SBC-T3530, SBC-T3730 and SBC-T3517. Signed-off-by:
Dmitry Lifshitz <lifshitz@compulab.co.il> Acked-by:
Igor Grinberg <grinberg@compulab.co.il> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Sebastian Andrzej Siewior authored
Cc: devicetree@vger.kernel.org Reviewed-by:
Tony Lindgren <tony@atomide.com> Tested-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Sebastian Andrzej Siewior authored
Cc: devicetree@vger.kernel.org Reviewed-by:
Tony Lindgren <tony@atomide.com> Tested-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Suman Anna authored
The '#mbox-cells' property is added to all the OMAP mailbox nodes. This property is mandatory with the new mailbox framework. Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Suman Anna authored
Add the interrupts property to all the 13 mailbox nodes in DRA7xx. The interrupts property information added is inline with the expected values with the DRA7xx crossbar driver, and is common to both DRA74x and DRA72x SoCs. Do note that the mailbox 1 is only capable of generating out 3 interrupts, while all the remaining mailboxes have 4 interrupts each. Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Nov 04, 2014
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Tony Lindgren authored
Looks like we have some GPMC NAND timings missing device width. This fixes "gpmc_cs_program_settings: invalid width 0!" errors during boot. Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
With the GPMC warnings now enabled, I noticed the LAN9220 timings can overflow the GPMC registers with 200MHz L3 speed. Earlier we were just skipping the bad timings and would continue with the bootloader timings. Now we no longer allow to continue with bad timings as we have the timings in the .dts files. We could start using the GPMC clock divider, but let's instead use the u-boot timings that are known to be working and a bit faster. These are basically the u-boot NET_GPMC_CONFIG[1-6] defines deciphered. Except that we don't set gpmc,burst-length as that's only partially configured and does not seem to work if fully enabled. [tony@atomide.com: updated to remove gpmc,burst-length] Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Oct 30, 2014
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Tony Lindgren authored
The four port serial port on the zoom debug board uses a TL16CP754C with a single interrupt and GPMC chip select. The serial ports each use a 8 bytes for IO registers, and are 256 bytes apart on the GPMC line. Let's add timings for all four ports so we can remove the GPMC workarounds for using bootloader timings. Not caused by this patch, but looks like u-boot only properly initializes the fifo on the first serial port. Currently the other ports produce garbage at least with my version of u-boot. I suspect that TL16CP754C needs non-standard initialization added to 8250 driver to properly fix this issue. Cc: Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
Let's use the bootloader values except for the partially configured wait-pin that does not seem to work. Cc: Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
The GPMC binding is obviously very confusing as the values are all over the place. People seem to confuse the GPMC partition size for the chip select, and the device IO size within the GPMC partition easily. The ranges entry contains the GPMC partition size. And the reg entry contains the size of the IO registers of the device connected to the GPMC. Let's fix the issue according to the following table: Device GPMC partition size Device IO size connected in the ranges entry in the reg entry NAND 0x01000000 (16MB) 4 16550 0x01000000 (16MB) 8 smc91x 0x01000000 (16MB) 0xf smc911x 0x01000000 (16MB) 0xff OneNAND 0x01000000 (16MB) 0x20000 (128KB) 16MB NOR 0x01000000 (16MB) 0x01000000 (16MB) 32MB NOR 0x02000000 (32MB) 0x02000000 (32MB) 64MB NOR 0x04000000 (64MB) 0x04000000 (64MB) 128MB NOR 0x08000000 (128MB) 0x08000000 (128MB) 256MB NOR 0x10000000 (256MB) 0x10000000 (256MB) Let's also add comments to the fixed entries while at it. Acked-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
Apparently some versions of nolo don't mux the all the necessary GPMC pins for the smc91x probe to work properly. Let's fix this issue by adding mux support for GPMC to the kernel. Note that GPMC clk needs input enabled for OnenNAND to work. Cc: Kevin Hilman <khilman@kernel.org> Cc: Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Oct 27, 2014
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds authored
Pull ARM SoC fixes from Olof Johansson: "Another week, another small batch of fixes. Most of these make zynq, socfpga and sunxi platforms work a bit better: - due to new requirements for regulators, DWMMC on socfpga broke past v3.17 - SMP spinup fix for socfpga - a few DT fixes for zynq - another option (FIXED_REGULATOR) for sunxi is needed that used to be selected by other options but no longer is. - a couple of small DT fixes for at91 - ...and a couple for i.MX" * tag 'armsoc-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: dts: imx28-evk: Let i2c0 run at 100kHz ARM: i.MX6: Fix "emi" clock name typo ARM: multi_v7_defconfig: enable CONFIG_MMC_DW_ROCKCHIP ARM: sunxi_defconfig: enable CONFIG_REGULATOR_FIXED_VOLTAGE ARM: dts: socfpga: Add a 3.3V fixed regulator node ARM: dts: socfpga: Fix SD card detect ARM: dts: socfpga: rename gpio nodes ARM: at91/dt: sam9263: fix PLLB frequencies power: reset: at91-reset: fix power down register MAINTAINERS: add atmel ssc driver maintainer entry arm: socfpga: fix fetching cpu1start_addr for SMP ARM: zynq: DT: trivial: Fix mc node ARM: zynq: DT: Add cadence watchdog node ARM: zynq: DT: Add missing reference for memory-controller ARM: zynq: DT: Add missing reference for ADC ARM: zynq: DT: Add missing address for L2 pl310 ARM: zynq: DT: Remove 222 MHz OPP ARM: zynq: DT: Fix GEM register area size
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git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfsLinus Torvalds authored
Pull vfs updates from Al Viro: "overlayfs merge + leak fix for d_splice_alias() failure exits" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: overlayfs: embed middle into overlay_readdir_data overlayfs: embed root into overlay_readdir_data overlayfs: make ovl_cache_entry->name an array instead of pointer overlayfs: don't hold ->i_mutex over opening the real directory fix inode leaks on d_splice_alias() failure exits fs: limit filesystem stacking depth overlay: overlay filesystem documentation overlayfs: implement show_options overlayfs: add statfs support overlay filesystem shmem: support RENAME_WHITEOUT ext4: support RENAME_WHITEOUT vfs: add RENAME_WHITEOUT vfs: add whiteout support vfs: export check_sticky() vfs: introduce clone_private_mount() vfs: export __inode_permission() to modules vfs: export do_splice_direct() to modules vfs: add i_op->dentry_open()
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- Oct 26, 2014
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Olof Johansson authored
Merge tag 'imx-fixes-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes Merge "ARM: imx: fixes for 3.18" from Shawn Guo: The i.MX fixes for 3.18: - Revert one patch which increases I2C bus frequency on imx28-evk - Fix a typo on imx6q EIM clock name * tag 'imx-fixes-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx28-evk: Let i2c0 run at 100kHz ARM: i.MX6: Fix "emi" clock name typo Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Oct 25, 2014
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Fabio Estevam authored
Commit 78b81f46 ("ARM: dts: imx28-evk: Run I2C0 at 400kHz") caused issues when doing the following sequence in loop: - Boot the kernel - Perform audio playback - Reboot the system via 'reboot' command In many times the audio card cannot be probed, which causes playback to fail. After restoring to the original i2c0 frequency of 100kHz there is no such problem anymore. This reverts commit 78b81f46 . Cc: <stable@vger.kernel.org> # 3.16+ Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Steve Longerbeam authored
Fix a typo error, the "emi" names refer to the eim clocks. The change fixes typo in EIM and EIM_SLOW pre-output dividers and selectors clock names. Notably EIM_SLOW clock itself is named correctly. Signed-off-by:
Steve Longerbeam <steve_longerbeam@mentor.com> [vladimir_zapolskiy@mentor.com: ported to v3.17] Signed-off-by:
Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Al Viro authored
same story... Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk>
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Al Viro authored
no sense having it a pointer - all instances have it pointing to local variable in the same stack frame Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk>
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Al Viro authored
Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk>
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Al Viro authored
just use it to serialize the assignment Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk>
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git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds authored
Pull MIPS fixes from Ralf Baechle: "This is the first round of fixes and tying up loose ends for MIPS. - plenty of fixes for build errors in specific obscure configurations - remove redundant code on the Lantiq platform - removal of a useless SEAD I2C driver that was causing a build issue - fix an earlier TLB exeption handler fix to also work on Octeon. - fix ISA level dependencies in FPU emulator's instruction decoding. - don't hardcode kernel command line in Octeon software emulator. - fix an earlier fix for the Loondson 2 clock setting" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: SEAD3: Fix I2C device registration. MIPS: SEAD3: Nuke PIC32 I2C driver. MIPS: ftrace: Fix a microMIPS build problem MIPS: MSP71xx: Fix build error MIPS: Malta: Do not build the malta-amon.c file if CMP is not enabled MIPS: Prevent compiler warning from cop2_{save,restore} MIPS: Kconfig: Add missing MIPS_CPS dependencies to PM and cpuidle MIPS: idle: Remove leftover __pastwait symbol and its references MIPS: Sibyte: Include the swarm subdir to the sb1250 LittleSur builds MIPS: ptrace.h: Add a missing include MIPS: ath79: Fix compilation error when CONFIG_PCI is disabled MIPS: MSP71xx: Remove compilation error when CONFIG_MIPS_MT is present MIPS: Octeon: Remove special case for simulator command line. MIPS: tlbex: Properly fix HUGE TLB Refill exception handler MIPS: loongson2_cpufreq: Fix CPU clock rate setting mismerge pci: pci-lantiq: remove duplicate check on resource MIPS: Lasat: Add missing CONFIG_PROC_FS dependency to PICVUE_PROC MIPS: cp1emu: Fix ISA restrictions for cop1x_op instructions
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git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds authored
Pull arm64 fixes from Catalin Marinas: - enable 48-bit VA space now that KVM has been fixed, together with a couple of fixes for pgd allocation alignment and initial memblock current_limit. There is still a dependency on !ARM_SMMU which needs to be updated as it uses the page table manipulation macros of the host kernel - eBPF fixes following changes/conflicts during the merging window - Compat types affecting compat_elf_prpsinfo - Compilation error on UP builds - ASLR fix when /proc/sys/kernel/randomize_va_space == 0 - DT definitions for CLCD support on ARMv8 model platform * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Fix memblock current_limit with 64K pages and 48-bit VA arm64: ASLR: Don't randomise text when randomise_va_space == 0 arm64: vexpress: Add CLCD support to the ARMv8 model platform arm64: Fix compilation error on UP builds Documentation/arm64/memory.txt: fix typo net: bpf: arm64: minor fix of type in jited arm64: bpf: add 'load 64-bit immediate' instruction arm64: bpf: add 'shift by register' instructions net: bpf: arm64: address randomize and write protect JIT code arm64: mm: Correct fixmap pagetable types arm64: compat: fix compat types affecting struct compat_elf_prpsinfo arm64: Align less than PAGE_SIZE pgds naturally arm64: Allow 48-bits VA space without ARM_SMMU
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git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparcLinus Torvalds authored
Pull two sparc fixes from David Miller: 1) Fix boots with gcc-4.9 compiled sparc64 kernels. 2) Add missing __get_user_pages_fast() on sparc64 to fix hangs on futexes used in transparent hugepage areas. It's really idiotic to have a weak symbolled fallback that just returns zero, and causes this kind of bug. There should be no backup implementation and the link should fail if the architecture fails to provide __get_user_pages_fast() and supports transparent hugepages. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc64: Implement __get_user_pages_fast(). sparc64: Fix register corruption in top-most kernel stack frame during boot.
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git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds authored
Pull kvm fixes from Paolo Bonzini: "This is a pretty large update. I think it is roughly as big as what I usually had for the _whole_ rc period. There are a few bad bugs where the guest can OOPS or crash the host. We have also started looking at attack models for nested virtualization; bugs that usually result in the guest ring 0 crashing itself become more worrisome if you have nested virtualization, because the nested guest might bring down the non-nested guest as well. For current uses of nested virtualization these do not really have a security impact, but you never know and bugs are bugs nevertheless. A lot of these bugs are in 3.17 too, resulting in a large number of stable@ Ccs. I checked that all the patches apply there with no conflicts" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: kvm: vfio: fix unregister kvm_device_ops of vfio KVM: x86: Wrong assertion on paging_tmpl.h kvm: fix excessive pages un-pinning in kvm_iommu_map error path. KVM: x86: PREFETCH and HINT_NOP should have SrcMem flag KVM: x86: Emulator does not decode clflush well KVM: emulate: avoid accessing NULL ctxt->memopp KVM: x86: Decoding guest instructions which cross page boundary may fail kvm: x86: don't kill guest on unknown exit reason kvm: vmx: handle invvpid vm exit gracefully KVM: x86: Handle errors when RIP is set during far jumps KVM: x86: Emulator fixes for eip canonical checks on near branches KVM: x86: Fix wrong masking on relative jump/call KVM: x86: Improve thread safety in pit KVM: x86: Prevent host from panicking on shared MSR writes. KVM: x86: Check non-canonical addresses upon WRMSR
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