- Mar 01, 2016
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Lokesh Vutla authored
DRA7 SoC has the capability to support DDR memory upto 4GB. In order to represent this in memory dt node, the address-cells and size cells should be 2. So, changing the address-cells and size-cells to 2 and updating the memory nodes accordingly. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Paul Kocialkowski authored
This adds support for USB OTG on the Optimus Black. The HSUSB0 interface is connected to the TWL4030 USB PHY. Signed-off-by:
Paul Kocialkowski <contact@paulk.fr> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Paul Kocialkowski authored
The LG Optimus Black codename sniper is a smartphone that was designed and manufactured by LG Electronics (LGE) and released back in 2011. It is using an OMAP3630 SoC, GP version. This adds devicetree support for the device, with only a few basic features supported, such as debug uart, i2c, internal emmc and external mmc. Signed-off-by:
Paul Kocialkowski <contact@paulk.fr> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Feb 27, 2016
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Adam Ford authored
LogicPD has two main Torpedo styles, a version with wireless and a version without wireless. This version has Bluetooth and WiFi, but there really isn't an easy way to identify them automatically. This simply adds "Wireless" to the model to distinguish it from the 'base' model that will come soon. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
Add RTC entry for dm816x. Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
Add RTC entry for dm814x and dra62x. Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
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Roger Quadros authored
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and can't be used for wait state insertion for NAND I/O read/write. So disable read/write wait monitoring as per Reference Manual's suggestion [1]. [1] dm816x TRM: SPRUGX8C: 9.2.4.12.2 NAND Device-Ready Pin Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and can't be used for wait state insertion for NAND I/O read/write. So disable read/write wait monitoring as per Reference Manual's suggestion [1]. [1] AM335x TRM: SPRUH73L: 7.1.3.3.12.2 NAND Device-Ready Pin Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Ilya Ledvich <ilya@compulab.co.il> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Rostislav Lisovy <lisovy@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Ilya Ledvich <ilya@compulab.co.il> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Rostislav Lisovy <lisovy@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and can't be used for wait state insertion for NAND I/O read/write. So disable read/write wait monitoring as per Reference Manual's suggestion [1]. [1] AM437x TRM: SPRUHL7D: 9.1.3.3.12.2 NAND Device-Ready Pin Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
wait pin monitoring is not used for nand so it is pointless to have the gpmc,wait-monitoring-ns property. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Feb 23, 2016
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Nishanth Menon authored
Add EEPROM at 0x50 that describes the board configuration. This is useful for userspace programs that may need to check board revision and other similar information. Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Adam Ford authored
The Logic PD SOM-LV has a USB Host Controller connected to 3-port hub. This enables the pin muxing for the host controller and ehci-phy. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
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Pali Rohár authored
This makes DTS structure more readable. Signed-off-by:
Pali Rohár <pali.rohar@gmail.com> Acked-By:
Sebastian Reichel <sre@kernel.org> Acked-by:
Pavel Machek <pavel@ucw.cz> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Adam Ford authored
The Logic PD DM37xx SOM-LV devkit consists of a base board and a SOM. While the SOM (System on Module) supports Bluetooth and WiFi, LPD did not obtain an FCC ID, so anyone who uses it will have to go through certification. I have only tested the Type 28 Display, SMSC9211 Ethernet, SD/MMC and basic power management, however the overall current seems high. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Adam Ford authored
The backlight pin is shared with Timer 10 PWM. This patch allows the pwm_bl driver to enable the pwm run by this timer to dim the backlight. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Ivaylo Dimitrov authored
Add linux,can-disable; to all gpios exported from gpio-keys driver, so userspace can disable them Signed-off-by:
Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Feb 20, 2016
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Keerthy authored
The SoCs on am43x-epos-evm are named am438x. Hence add the compatibility string and remove the am4372 string. Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Feb 13, 2016
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Keerthy authored
OMAP5 has 3 thermal zones cpu, core and multimedia. On the other hand DRA7 has 5 thermal zones cpu, gpu, core, dspeve and iva. Currently cpu, core and multimedia are being added via device tree and the other 2 are getting added via kernel. Add the missing thermal domains in device tree so we can create the zones with the appropriate trip numbers, type and temperatures. Signed-off-by:
Keerthy <j-keerthy@ti.com> Acked-by:
Eduardo Valentin <edubezval@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Keerthy authored
This patch changes a dtsi file to contain the thermal data for IVA domain. This data will enable a thermal shutdown at 125C. Signed-off-by:
Keerthy <j-keerthy@ti.com> Acked-by:
Eduardo Valentin <edubezval@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Keerthy authored
This patch changes a dtsi file to contain the thermal data for DSPEVE domain. This data will enable a thermal shutdown at 125C. Signed-off-by:
Keerthy <j-keerthy@ti.com> Acked-by:
Eduardo Valentin <edubezval@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Felipe Balbi authored
DWC3's tx-fifo-resize property has been deprecated because of it being unnecessary to any HW other than OMAP5 ES1.0. Signed-off-by:
Felipe Balbi <balbi@kernel.org> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Sebastian Reichel authored
This adds an idle pinctrl state, which will be used by the driver to avoid incoming data during clock rate changes or data flushing. Signed-off-By:
Sebastian Reichel <sre@kernel.org> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
The MCLK is provided by an external clock of 24.576MHz. Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
UART0 device is the device to be used for boot console output. Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Pau Pajuel authored
Provide RESET GPIO for the USB PHY, the USB Host port mode and the PHY device for the controller. Also provides pin multiplexer information for USB host pins. Signed-off-by:
Pau Pajuel <ppajuel@gmail.com> Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
UART3 device is the device to be used for boot console output. Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Adam Ford authored
This patch defines the pin muxing to configure the hsusb0 through the twl4030 PMIC, because we can't always assume the bootloader will do it correctly. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Sebastian Reichel authored
The Nokia N950 and Nokia N9 have a modem attached to their first ssi port. This change adds the modem to the SSI port. Signed-off-by:
Sebastian Reichel <sre@kernel.org> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Sebastian Reichel authored
The Nokia N950 and Nokia N9 have a modem attached to their first ssi port. This change adds all necessary information to initialize the SSI module, but does not yet add the modem information. Signed-off-by:
Sebastian Reichel <sre@kernel.org> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Adam Ford authored
The devkit has an AT25 EEPROM on MCSPI1. Enable this with default parameters. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Adam Ford authored
Setup regulator and fix pin muxing to allow Panel to sleep and wake from sleep for some low power improvements. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Adam Ford authored
The Wireless version of the SOM uses an AT24 EEPROM to store product ID. The EEPROM is readonly. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Adam Ford authored
The Logic PD Torpedo standard kits come with a SOM populated to us an 8-bit parallel camera interface. This patch pin muxes the omap3-isp pins, sets the MT9P031 clicks, and configures the i2c2 bus to communicate with the mt9p031 on address 0x48. I have not done a lot of testing, but when modprobing mt9p031, then omap3-isp, the board responds with MT9P031 detected at address 0x48. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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