- May 08, 2013
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Catalin Marinas authored
This patch adds the arm_pm_poweroff definition expected by the vexpress-poweroff.c driver and enables the latter for arm64. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Acked-by:
Pawel Moll <pawel.moll@arm.com>
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Catalin Marinas authored
This patch enables ARM_GIC on the arm64 kernel. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
* arm64-prep-gic: irqchip: gic: Perform the gic_secondary_init() call via CPU notifier irqchip: gic: Call handle_bad_irq() directly arm: Move chained_irq_(enter|exit) to a generic file arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
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- Apr 30, 2013
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Catalin Marinas authored
This patch changes the test_and_*_bit functions to use the load-acquire/store-release instructions instead of explicit DMB. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Mark Rutland authored
We're currently relying on unpredictable behaviour in our testops (test_and_*_bit), as stxr is unpredictable when the status register and the source register are the same This patch changes reallocates the status register so as to bring us back into the realm of predictable behaviour. Boot tested on an AEMv8 model. Signed-off-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Apr 26, 2013
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Catalin Marinas authored
This patch adds the necessary Kconfig entries to enable support for the ARMv8 software model (Versatile Express platform) together with the defconfig update. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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Pawel Moll authored
This patch adds the DTS files for the ARMv8 RTSM and Foundation models. Signed-off-by:
Pawel Moll <Pawel.Moll@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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Mark Rutland authored
Currently, if you pass the kernel a dtb where a cpu node has an unsupported enable-method property (e.g. "not-psci"), it'll explode horribly, as it iterates over the enable_ops array incorrectly. It increments the pointer *at* the current element, rather than incrementing the pointer *to* the current element. As the first two elements pointed to structures that were contiguous in memory, this happened to be equivalent. However the third element is NULL, so when the list is exhausted, smp_get_enable_ops generates the wrong pointer, and dereferences an arbitrary portion of memory, which currently happens to contain zero. This patch fixes this by indirecting the pointer one level, so we iterate over the array elements correctly, avoiding the below panic: Signed-off-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Steve Capper authored
show_pte makes use of the *_none_or_clear_bad style functions. If a pgd, pud or pmd is identified as being bad, it will then be cleared. As show_pte appears to be called from either the user or kernel fault handlers this side effect can lead to unpredictable behaviour; especially as TLB entries are not invalidated. This patch removes the page table sanitisation from show_pte. If a bad pgd, pud or pmd is encountered it is left unmodified. Signed-off-by:
Steve Capper <steve.capper@linaro.org> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The compat_stat structure doesn't match the arch/arm/ struct stat definition. This patch fixes the compat types and struct compat_stat definition accordingly. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Acked-by:
Will Deacon <will.deacon@arm.com>
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Catalin Marinas authored
The DSB following TLB or cache maintenance ops must be run on the same CPU. With kernel preemption enabled or for user-space cache maintenance this may not be the case. This patch adds an explicit DSB in the __switch_to() function. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Chen Gang authored
For compiling with allmodconfig, need vga.h file, so generate it which just only include the asm-generic one. It is firstly used by drivers/gpu/drm/drm_irq.c. The related error: include/video/vga.h:22:21: fatal error: asm/vga.h: No such file or directory Signed-off-by:
Chen Gang <gang.chen@asianux.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Will Deacon authored
For systems where the top 32-bits of the MPIDR are all zero, we should allow the device-tree to specify an #address-size of 0x1 for the CPU reg property and then zero extend the value there. Without this patch, kvmtool breaks with the recent mpidr parsing code introduced in 4c7aa002 ("arm64: kernel: initialise cpu_logical_map from the DT"). Acked-by:
Javi Merino <javi.merino@arm.com> Acked-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Apr 23, 2013
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Chen Gang authored
Drivers use cmpxchg64, cmpxchg64_local to perform 64-bit operation, so they can cross 32-bit and 64-bit platforms (it is a standard way). Signed-off-by:
Chen Gang <gang.chen@asianux.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Apr 19, 2013
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Chen Gang authored
when compiling with allmodconfig, CONFIG_64BIT=y the file drivers/base/regmap/regmap-mmio.c will use readq and writeq so we need implement these functions. Signed-off-by:
Chen Gang <gang.chen@asianux.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Apr 17, 2013
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Christopher Covington authored
For accurate accounting call contextidr_thread_switch before a task is scheduled, rather than after, when the 'next' variable has a different meaning since we switched the stacks. Signed-off-by:
Christopher Covington <cov@codeaurora.org> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Marc Zyngier authored
The ESR_EL1 decoding process is a bit cryptic, and KVM has also a need for the same constants. Add a new esr.h file containing the appropriate exception classes constants, and change entry.S to use it. Fix a small bug in the EL1 breakpoint check while we're at it. Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Mar 29, 2013
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Catalin Marinas authored
* arm64-klib: arm64: klib: Optimised atomic bitops arm64: klib: Optimised string functions arm64: klib: Optimised memory functions
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- Mar 27, 2013
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Catalin Marinas authored
All the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Acked-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Rob Herring <rob.herring@calxeda.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Tested-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Tested-by:
Dinh Nguyen <dinguyen@altera.com> Acked-by:
Nicolas Pitre <nico@linaro.org> Tested-by:
Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Barry Song <baohua.song@csr.com>
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Catalin Marinas authored
Previously, the gic_handle_cascade_irq() function was calling the ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after acquiring the desk->lock. Locking the cascaded IRQ desc is not needed for error reporting, so just call handle_bad_irq() directly. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Tested-by:
Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com>
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Catalin Marinas authored
These functions have been introduced by commit 10a8c383 (irq: introduce entry and exit functions for chained handlers) in asm/mach/irq.h. This patch moves them to linux/irqchip/chained_irq.h so that generic irqchip drivers do not rely on architecture specific header files. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Tested-by:
Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com>
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Catalin Marinas authored
This patch prepares the removal of <asm/mach/irq.h> include in the GIC and VIC irqchip drivers. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Tested-by:
Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com>
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Catalin Marinas authored
This patch uses the generic irqchip_init() function for initialising the interrupt controller on arm64. It also adds several definitions required by the ARM GIC irqchip driver but does not enable ARM_GIC yet. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Mar 26, 2013
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Liviu Dudau authored
With the (re)introduction of cpu_logical_map in arm64 we switch to the use of MPIDR values to identify CPUs. Update the psci code to do that. Signed-off-by:
Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Mar 22, 2013
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Catalin Marinas authored
This patch implements the AArch64-specific atomic bitops functions using exclusive memory accesses to avoid locking. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch introduces AArch64-specific string functions (strchr, strrchr). Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch introduces AArch64-specific memory functions (memcpy, memmove, memchr, memset). These functions are not optimised for any CPU implementation but can be used as a starting point once hardware is available. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Mar 21, 2013
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Javi Merino authored
The reg property of the cpu nodes in the DT now contains all the affinity levels in (MPIDR[39:32] and MPIDR[23:0]) and that's what boot_secondary() writes in the pen, so increase the mask in secondary_holding_pen accordingly. Signed-off-by:
Javi Merino <javi.merino@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Javi Merino authored
When booting the kernel, the cpu logical id map must be initialised using device tree data passed by FW or through an embedded blob. This patch parses the reg property in device tree "cpu" nodes, retrieves the corresponding CPUs hardware identifiers (MPIDR) and initialises the cpu logical map accordingly. The device tree HW identifiers are considered valid if all CPU nodes contain a "reg" property, there are no duplicate "reg" entries and the DT defines a CPU node whose "reg" property defines affinity levels that matches those of the boot CPU. The primary CPU is assigned cpu logical number 0 to keep the current convention valid. Based on a0ae0240 (ARM: kernel: add device tree init map function). Signed-off-by:
Javi Merino <javi.merino@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Javi Merino authored
Change the prototype of write_pen_release() accordingly and clarify that's holding the hardware id of the secondary that's going to boot. This is in preparation of getting HWIDs parsed from the DT. Signed-off-by:
Javi Merino <javi.merino@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
This patch adds an arch_initcall() for the of_clk_init() clock initialisation. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Anup Patel authored
This patch adds support for using earlyprintk with 8250/16550 UART ports. The 8250/16550 UART can either have 8-bit or 32-bit aligned registers which is HW vendor dependent. Kernel args for 8-bit aligned regs: earlyprintk=uart8250-8bit,<phys_address> Kernel args for 32-bit aligned regs: earlyprintk=uart8250-32bit,<phys_address> Signed-off-by:
Anup Patel <anup.patel@linaro.org> Reviewed-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Marc Zyngier authored
Enable early_printk to use the FastModel semihosting to output the early kernel messages. Works both for host and guest kernels. To use this feature, pass "early_printk=smh" to the kernel. Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Marc Zyngier authored
In order to preserve some kind of source compatibility between arm and arm64, introduce read_cpuid_{implementor,part_number,mpidr} which are used on KVM to find out which CPU we're running on. Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Mar 20, 2013
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Paul Bolle authored
The Kconfig entry for DEBUG_ERRORS is a verbatim copy of the former arm entry for that symbol. It got removed in v2.6.39 because it wasn't actually used anywhere. There are still no users of DEBUG_ERRORS so remove this entry too. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> [catalin.marinas@arm.com: removed option from defconfig] Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Mar 19, 2013
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Paul Bolle authored
Config option GENERIC_HARDIRQS_NO_DEPRECATED was removed in commit 78c89825 ("genirq: Remove the now obsolete config options and select statements"), but the select was accidentally reintroduced in commit 8c2c3df3 ("arm64: Build infrastructure"). Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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- Mar 18, 2013
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Andreas Schwab authored
The expression to compute the padding needed to fill the uc_sigmask field to 1024 bits actually computes the padding needed for 1080 bits. Fortunately, due to the 16-byte alignment of the following field (uc_mcontext) the definition in glibc contains enough bytes of padding after uc_sigmask so that the overall offsets and size match in both definitions. Signed-off-by:
Andreas Schwab <schwab@suse.de> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
The __atomic_hash is only defined when SMP is enabled but the arm64ksyms.c exports it even for the UP case. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas authored
Recent clean-up of the compat signal code left an unused 'stack' variable. Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com>
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Linus Torvalds authored
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