Commit e0eff721 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch... 


Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2018-04-30.for-upstream' into staging

edgar/xilinx-next-2018-01.for-upstream

# gpg: Signature made Mon 30 Apr 2018 15:52:35 BST
# gpg:                using RSA key 29C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>"
# gpg:                 aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>"
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF  4151 29C5 9678 0F6B CA83

* remotes/edgar/tags/edgar/xilinx-next-2018-04-30.for-upstream:
  target-microblaze: mmu: Make the TLBX MISS bit read-only
  target-microblaze: mmu: Make TLBSX write-only
  target-microblaze: Don't clobber the IMM reg for ld/st reversed
  target-microblaze: Fix trap checks for FPU insns
  target-microblaze: Respect MSR.PVR as read-only

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents c2c76850 fce6a8ec

target/microblaze/mmu.c

+8 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ done: 
uint32_t mmu_read(CPUMBState *env, uint32_t rn)

{

    unsigned int i;

    uint32_t r;

    uint32_t r = 0;



    if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {

        qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
@@ -211,6 +211,9 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) 
            }

            r = env->mmu.regs[rn];

            break;

        case MMU_R_TLBSX:

            qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n");

            break;

        default:

            r = env->mmu.regs[rn];

            break;
@@ -270,6 +273,10 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) 
                env->mmu.regs[rn] = v;

            }

            break;

        case MMU_R_TLBX:

            /* Bit 31 is read-only.  */

            env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);

            break;

        case MMU_R_TLBSX:

        {

            struct microblaze_mmu_lookup lu;

target/microblaze/translate.c

+2 −4
Original line number Diff line number Diff line
@@ -424,7 +424,7 @@ static inline void msr_write(DisasContext *dc, TCGv v) 
    /* PVR bit is not writable.  */

    tcg_gen_andi_tl(t, v, ~MSR_PVR);

    tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);

    tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);

    tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t);

    tcg_temp_free(t);

}
@@ -952,7 +952,6 @@ static void dec_load(DisasContext *dc) 
                tcg_gen_sub_tl(low, tcg_const_tl(3), low);

                tcg_gen_andi_tl(t, t, ~3);

                tcg_gen_or_tl(t, t, low);

                tcg_gen_mov_tl(env_imm, t);

                tcg_temp_free(low);

                break;

            }
@@ -1104,7 +1103,6 @@ static void dec_store(DisasContext *dc) 
                tcg_gen_sub_tl(low, tcg_const_tl(3), low);

                tcg_gen_andi_tl(t, t, ~3);

                tcg_gen_or_tl(t, t, low);

                tcg_gen_mov_tl(env_imm, t);

                tcg_temp_free(low);

                break;

            }
@@ -1412,7 +1410,7 @@ static void dec_fpu(DisasContext *dc) 


    if ((dc->tb_flags & MSR_EE_FLAG)

          && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)

          && (dc->cpu->cfg.use_fpu != 1)) {

          && !dc->cpu->cfg.use_fpu) {

        tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);

        t_gen_raise_exception(dc, EXCP_HW_EXCP);

        return;