Commit 81dbcfa9 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190215' into staging 



target-arm queue:
 * gdbstub: Send a reply to the vKill packet
 * Improve codegen for neon min/max and saturating arithmetic
 * Fix a bug in clearing FPSCR exception status bits
 * hw/arm/armsse: Fix miswiring of expansion IRQs
 * hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
 * MAINTAINERS: Remove Peter Crosthwaite from various entries
 * arm: Allow system registers for KVM guests to be changed by QEMU code
 * linux-user: support HWCAP_CPUID which exposes ID registers to user code
 * Fix bug in 128-bit cmpxchg for BE Arm guests
 * Implement (no-op) HACR_EL2
 * Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

# gpg: Signature made Fri 15 Feb 2019 10:19:14 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190215: (25 commits)
  gdbstub: Send a reply to the vKill packet.
  target/arm: Add missing clear_tail calls
  target/arm: Use vector operations for saturation
  target/arm: Split out FPSCR.QC to a vector field
  target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
  target/arm: Split out flags setting from vfp compares
  target/arm: Fix arm_cpu_dump_state vs FPSCR
  target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
  target/arm: Remove neon min/max helpers
  target/arm: Use tcg integer min/max primitives for neon
  target/arm: Use vector minmax expanders for aarch32
  target/arm: Use vector minmax expanders for aarch64
  target/arm: Rely on optimization within tcg_gen_gvec_or
  hw/arm/armsse: Fix miswiring of expansion IRQs
  hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
  MAINTAINERS: Remove Peter Crosthwaite from various entries
  arm: Allow system registers for KVM guests to be changed by QEMU code
  linux-user/elfload: enable HWCAP_CPUID for AArch64
  target/arm: expose remaining CPUID registers as RAZ
  target/arm: expose MPIDR_EL1 to userspace
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 0266c739 0f8b09b2

MAINTAINERS

+0 −4
Original line number Diff line number Diff line
@@ -110,7 +110,6 @@ Guest CPU cores (TCG): 
----------------------

Overall

L: qemu-devel@nongnu.org

M: Peter Crosthwaite <crosthwaite.peter@gmail.com>

M: Richard Henderson <rth@twiddle.net>

R: Paolo Bonzini <pbonzini@redhat.com>

S: Maintained
@@ -1345,7 +1344,6 @@ F: tests/virtio-scsi-test.c 
T: git https://github.com/bonzini/qemu.git scsi-next



SSI

M: Peter Crosthwaite <crosthwaite.peter@gmail.com>

M: Alistair Francis <alistair@alistair23.me>

S: Maintained

F: hw/ssi/*
@@ -1356,7 +1354,6 @@ F: tests/m25p80-test.c 


Xilinx SPI

M: Alistair Francis <alistair@alistair23.me>

M: Peter Crosthwaite <crosthwaite.peter@gmail.com>

S: Maintained

F: hw/ssi/xilinx_*
@@ -1766,7 +1763,6 @@ F: qom/cpu.c 
F: include/qom/cpu.h



Device Tree

M: Peter Crosthwaite <crosthwaite.peter@gmail.com>

M: Alexander Graf <agraf@suse.de>

S: Maintained

F: device_tree.c

gdbstub.c

+1 −0
Original line number Diff line number Diff line
@@ -1361,6 +1361,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) 
            break;

        } else if (strncmp(p, "Kill;", 5) == 0) {

            /* Kill the target */

            put_packet(s, "OK");

            error_report("QEMU: Terminated via GDBstub");

            exit(0);

        } else {

hw/arm/armsse.c

+1 −1
Original line number Diff line number Diff line
@@ -565,7 +565,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) 
        /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */

        s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);

        for (j = 0; j < s->exp_numirq; j++) {

            s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, i + 32);

            s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32);

        }

        if (i == 0) {

            gpioname = g_strdup("EXP_IRQ");

hw/intc/armv7m_nvic.c

+2 −2
Original line number Diff line number Diff line
@@ -1841,7 +1841,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, 
            }

        }

        break;

    case 0xd18: /* System Handler Priority (SHPR1) */

    case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */

        if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {

            val = 0;

            break;
@@ -1956,7 +1956,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 
        }

        nvic_irq_update(s);

        return MEMTX_OK;

    case 0xd18: /* System Handler Priority (SHPR1) */

    case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */

        if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {

            return MEMTX_OK;

        }

linux-user/elfload.c

+1 −0
Original line number Diff line number Diff line
@@ -580,6 +580,7 @@ static uint32_t get_elf_hwcap(void) 


    hwcaps |= ARM_HWCAP_A64_FP;

    hwcaps |= ARM_HWCAP_A64_ASIMD;

    hwcaps |= ARM_HWCAP_A64_CPUID;



    /* probe for the extra features */

#define GET_FEATURE_ID(feat, hwcap) \