Commit 0266c739 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' into staging 



MIPS queue for February 14th, 2019

# gpg: Signature made Thu 14 Feb 2019 16:48:39 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-feb-14-2019:
  tests/tcg: target/mips: Add tests for MSA logic instructions
  tests/tcg: target/mips: Add wrappers for MSA logic instructions
  tests/tcg: target/mips: Add tests for MSA interleave instructions
  tests/tcg: target/mips: Add wrappers for MSA interleave instructions
  tests/tcg: target/mips: Add tests for MSA bit counting instructions
  tests/tcg: target/mips: Add wrappers for MSA bit counting instructions
  tests/tcg: target/mips: Add a header with test utilities
  tests/tcg: target/mips: Add a header with test inputs
  tests/tcg: target/mips: Remove an unnecessary file
  target/mips: introduce MTTCG-enabled builds
  hw/mips_cpc: kick a VP when putting it into Run statewq
  target/mips: hold BQL in mips_vpe_wake()
  hw/mips_int: hold BQL for all interrupt requests
  target/mips: reimplement SC instruction emulation and use cmpxchg
  target/mips: compare virtual addresses in LL/SC sequence

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 0d3e41d5 ba632924

configure

+3 −0
Original line number Diff line number Diff line
@@ -7203,11 +7203,13 @@ case "$target_name" in 
    target_compiler=$cross_cc_microblaze

  ;;

  mips|mipsel)

    mttcg="yes"

    TARGET_ARCH=mips

    target_compiler=$cross_cc_mips

    echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak

  ;;

  mipsn32|mipsn32el)

    mttcg="yes"

    TARGET_ARCH=mips64

    TARGET_BASE_ARCH=mips

    target_compiler=$cross_cc_mipsn32
@@ -7215,6 +7217,7 @@ case "$target_name" in 
    echo "TARGET_ABI32=y" >> $config_target_mak

  ;;

  mips64|mips64el)

    mttcg="yes"

    TARGET_ARCH=mips64

    TARGET_BASE_ARCH=mips

    target_compiler=$cross_cc_mips64

hw/mips/mips_int.c

+12 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
 */



#include "qemu/osdep.h"

#include "qemu/main-loop.h"

#include "hw/hw.h"

#include "hw/mips/cpudevs.h"

#include "cpu.h"
@@ -32,10 +33,17 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) 
    MIPSCPU *cpu = opaque;

    CPUMIPSState *env = &cpu->env;

    CPUState *cs = CPU(cpu);

    bool locked = false;



    if (irq < 0 || irq > 7)

        return;



    /* Make sure locking works even if BQL is already held by the caller */

    if (!qemu_mutex_iothread_locked()) {

        locked = true;

        qemu_mutex_lock_iothread();

    }



    if (level) {

        env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
@@ -56,6 +64,10 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) 
    } else {

        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);

    }



    if (locked) {

        qemu_mutex_unlock_iothread();

    }

}



void cpu_mips_irq_init_cpu(MIPSCPU *cpu)

hw/misc/mips_cpc.c

+15 −2
Original line number Diff line number Diff line
@@ -30,6 +30,14 @@ static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc) 
    return (1ULL << cpc->num_vp) - 1;

}



static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)

{

    MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr;



    cpu_reset(cs);

    cpc->vp_running |= 1ULL << cs->cpu_index;

}



static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)

{

    CPUState *cs = first_cpu;
@@ -37,8 +45,13 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) 
    CPU_FOREACH(cs) {

        uint64_t i = 1ULL << cs->cpu_index;

        if (i & vp_run & ~cpc->vp_running) {

            cpu_reset(cs);

            cpc->vp_running |= i;

            /*

             * To avoid racing with a CPU we are just kicking off.

             * We do the final bit of preparation for the work in

             * the target CPUs context.

             */

            async_safe_run_on_cpu(cs, mips_cpu_reset_async_work,

                                  RUN_ON_CPU_HOST_PTR(cpc));

        }

    }

}

linux-user/mips/cpu_loop.c

+0 −73
Original line number Diff line number Diff line
@@ -392,70 +392,6 @@ static const uint8_t mips_syscall_args[] = { 
#  undef MIPS_SYS

# endif /* O32 */



static int do_store_exclusive(CPUMIPSState *env)

{

    target_ulong addr;

    target_ulong page_addr;

    target_ulong val;

    uint32_t val_wp = 0;

    uint32_t llnewval_wp = 0;

    int flags;

    int segv = 0;

    int reg;

    int d;

    int wp;



    addr = env->lladdr;

    page_addr = addr & TARGET_PAGE_MASK;

    start_exclusive();

    mmap_lock();

    flags = page_get_flags(page_addr);

    if ((flags & PAGE_READ) == 0) {

        segv = 1;

    } else {

        reg = env->llreg & 0x1f;

        d = (env->llreg & 0x20) != 0;

        wp = (env->llreg & 0x40) != 0;

        if (!wp) {

            if (d) {

                segv = get_user_s64(val, addr);

            } else {

                segv = get_user_s32(val, addr);

            }

        } else {

            segv = get_user_s32(val, addr);

            segv |= get_user_s32(val_wp, addr);

            llnewval_wp = env->llnewval_wp;

        }

        if (!segv) {

            if (val != env->llval && val_wp == llnewval_wp) {

                env->active_tc.gpr[reg] = 0;

            } else {

                if (!wp) {

                    if (d) {

                        segv = put_user_u64(env->llnewval, addr);

                    } else {

                        segv = put_user_u32(env->llnewval, addr);

                    }

                } else {

                    segv = put_user_u32(env->llnewval, addr);

                    segv |= put_user_u32(env->llnewval_wp, addr + 4);

                }

                if (!segv) {

                    env->active_tc.gpr[reg] = 1;

                }

            }

        }

    }

    env->lladdr = -1;

    if (!segv) {

        env->active_tc.PC += 4;

    }

    mmap_unlock();

    end_exclusive();

    return segv;

}



/* Break codes */

enum {

    BRK_OVERFLOW = 6,
@@ -597,15 +533,6 @@ done_syscall: 
            info.si_code = TARGET_TRAP_BRKPT;

            queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);

            break;

        case EXCP_SC:

            if (do_store_exclusive(env)) {

                info.si_signo = TARGET_SIGSEGV;

                info.si_errno = 0;

                info.si_code = TARGET_SEGV_MAPERR;

                info._sifields._sigfault._addr = env->active_tc.PC;

                queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);

            }

            break;

        case EXCP_DSPDIS:

            info.si_signo = TARGET_SIGILL;

            info.si_errno = 0;

target/mips/cpu.h

+4 −5
Original line number Diff line number Diff line
@@ -11,6 +11,8 @@ 
#include "exec/cpu-defs.h"

#include "fpu/softfloat.h"



#define TCG_GUEST_DEFAULT_MO (0)



struct CPUMIPSState;



typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
@@ -867,18 +869,17 @@ struct CPUMIPSState { 
#define CP0C5_NFExists     0

    int32_t CP0_Config6;

    int32_t CP0_Config7;

    uint64_t CP0_LLAddr;

    uint64_t CP0_MAAR[MIPS_MAAR_MAX];

    int32_t CP0_MAARI;

    /* XXX: Maybe make LLAddr per-TC? */

/*

 * CP0 Register 17

 */

    uint64_t lladdr;

    target_ulong lladdr; /* LL virtual address compared against SC */

    target_ulong llval;

    target_ulong llnewval;

    uint64_t llval_wp;

    uint32_t llnewval_wp;

    target_ulong llreg;

    uint64_t CP0_LLAddr_rw_bitmask;

    int CP0_LLAddr_shift;

/*
@@ -1155,8 +1156,6 @@ enum { 


    EXCP_LAST = EXCP_TLBRI,

};

/* Dummy exception for conditional stores.  */

#define EXCP_SC 0x100



/*

 * This is an internally generated WAKE request line.