Unverified Commit 087b051a authored by Jonathan Behrens's avatar Jonathan Behrens Committed by Palmer Dabbelt
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target/riscv: More accurate handling of `sip` CSR 



According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zero. This patch implements both of those requirements.

Signed-off-by: default avatarJonathan Behrens <jonathan@fintelia.io>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 4cc16b3b

target/riscv/csr.c

+5 −2
Original line number Diff line number Diff line
@@ -237,6 +237,7 @@ static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | 
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |

    SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |

    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;

static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;



#if defined(TARGET_RISCV32)

static const char valid_vm_1_09[16] = {
@@ -682,8 +683,10 @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) 
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,

                   target_ulong new_value, target_ulong write_mask)

{

    return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,

                   write_mask & env->mideleg);

    int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,

                      write_mask & env->mideleg & sip_writable_mask);

    *ret_value &= env->mideleg;

    return ret;

}



/* Supervisor Protection and Translation */