- Jan 29, 2013
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Lucas Stach authored
This adds the device tree include file for the Toradex Colibri T20 Computer on Module (COM). It's only valid for the 512MB RAM version of the module, as the 256MB version needs different EMC tables and flash configuration. To make this clear the suffix -512 was added to the board compatible string. The Colibri T20 uses a Tegra20 SoC and has onboard USB Ethernet and AC97 sound. Still some things like onboard NAND support missing, but should be a good base for further development. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Lucas Stach authored
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
Enable Tegra based keyboard interfacing for keys and provide all key mapping through DTS file. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
Enable Tegra based keyboard controller and populate the key mapping for Whistler. With this patch, HOME, BACK, POWER and MENU keys will work. Still other keys which are in ROW3 and ROW4 will not work as it conflicts with KBC pins on SDIO2 pinmux. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
UARTC is used for the interfacing with bluetooth device. Register this UART channel as high speed serial channel so that it can use the APB DMA for data transfer. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
Enable Tegra based keyboard controller and populate the key matrix for seaboard. The key matrix was originally on driver code which is removed to have clean driver. The key mapping is now passed through dts file. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: added clocks property] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
This ensures nodes are sorted in order of reg address. This makes it easier to compare against e.g. the U-Boot device trees, and is simply consistent and clean. While we're at it, remove the unit address from the cache-controller node name, since it's unique without it. Reported-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Lucas Stach authored
Add default entry for the AC97 host controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Bryan Wu authored
This patch adds support for Tegra30 Beaver board in upstream kernel. Beaver board is a Tegra30 SoC based development board, it has following features: - T30 or T33 SoC (Qual core ARM Cortex A9) - 2 GB DDR3L - 16 GB EMMC - 1 SD slot - 1 USB Standart A port and 1 USB micro AB port - PCI-E Gig Ethernet - Audio input/output - SATA port - HDMI output - UART and JTAG Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
... and disable tri-state from the pingroup that contains the poweroff GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Bryan Wu authored
Use engineering name 'Tegra20' instead of 'Tegra2' Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
tegra30 gpio controller is not compatible with the tegra20 due to their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30 bank stride is 0x100. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed typo syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add new Tegra 114 SoC support. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add a new evaluation board, Pluto for Tegra 114 family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add a new evaluation board, Dalmore for Tegra 114 family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add tegra_chip_id TEGRA114 0x35 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes. For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The patch to add USB PHY nodes to device tree was written before Tegra supported the clocks property in device tree. Now that it does, add the required clocks properties to these nodes. This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced by clk_get(phy->dev, clock_name), as part of converting the PHY driver to a platform driver. Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Venu Byravarasu authored
Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Venu Byravarasu authored
As Tegra USB host driver is using instance number for resetting PORT0 twice, adding a new DT property for handling this. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Venu Byravarasu authored
USB register base address and sizes defined in iomap.h are not used in any files other than board-dt-tegra20.c. Hence removed those defines from header file and using the absolute values in board files. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Remove AUXDATA as clocks are initialized from device node. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Remove AUXDATA as clock are initialized from device node. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock i2c clock information to device node. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: added second clock to 3d node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Remove all legacy clock code from mach-tegra. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Migrate Tegra clock support to drivers/clk/tegra, this involves moving: 1. definition of tegra_cpu_car_ops to clk.c 2. definition of reset functions to clk-peripheral.c 3. change parent of cpu clock. 4. Remove legacy clock initialization. 5. Initialize clocks using DT. 6. Remove all instance of mach/clk.h Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: use to_clk_periph_gate().] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
The device tree binding models Tegra30 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: fixed typo in binding doc] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The Tegra20 CAR (Clock And Reset) Controller controls most aspects of most clocks within Tegra20. The device tree binding models this as a single monolithic clock provider, which exports many clocks. This reduces the number of nodes needed in device tree to represent these clocks. This binding is only useful for Tegra20; the set of clocks that exists on Tegra30 is sufficiently different to merit its own binding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> [pgaikwad: Added mux clk ids and sorted CAR node] Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra. Move the tegra_cpu_car_ops to include/linux/clk/tegra.h. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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