- May 20, 2015
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https://github.com/Xilinx/linux-xlnxArnd Bergmann authored
Merge "arm: Xilinx Zynq SoC patches for v4.2" from Michal Simek: - Change SoC reset path - Fix SLCR unlock scheme * tag 'zynq-soc-for-4.2' of https://github.com/Xilinx/linux-xlnx: ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart ARM: zynq: Use restart_handler mechanism for slcr reset
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Arnd Bergmann authored
This makes uniphier behave like all the other platforms that support TWD, and only select this driver when SMP is enabled. Without this, we get a compile error on UP builds: arch/arm/kernel/smp_twd.c: In function 'twd_local_timer_of_register': arch/arm/kernel/smp_twd.c:391:20: error: 'setup_max_cpus' undeclared (first use in this function) Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Masahiro Yamada <yamada.masahiro@socionext.com>
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Joachim Eastwood authored
Using a dedicated symbol for low-level debugging instead of the arch symbol will make this platform play nice when enabled on a kernel that supports multiple platforms. Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Joachim Eastwood authored
Add a MAINTAINER entry covering all NXP LPC18xx/43xx machine and drivers files. Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- May 18, 2015
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Josh Cartwright authored
The SLCR is unconditionally unlocked early on boot in zynq_slcr_init() and not ever re-locked. As such, it is not necessary to explicitly unlock in the restart codepath. Signed-off-by:
Josh Cartwright <joshc@ni.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Josh Cartwright authored
By making use of the restart_handler chain mechanism, the SLCR-based reset mechanism can be prioritized amongst other mechanisms available on a particular board. Choose a default high-ish priority of 192 for this restart mechanism. Signed-off-by:
Josh Cartwright <joshc@ni.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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- May 16, 2015
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Maxime Coquelin authored
Add a MAINTAINER entry covering all STM32 machine and drivers files. Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Jun Nie authored
Add entry for ZTE ARM architecture Signed-off-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Jun Nie authored
Bring up the secondary core. Enable hotplug with supporting powering off secondary core. Signed-off-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Jun Nie authored
Use the UART0 peripheral for low level debug. Only the UART port 0 is currently supported. Signed-off-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Jun Nie authored
Add basic code for ZTE ZX296702 platform. [arnd: removed unused zx296702_init_machine function, and changed l2c aux val to default] Signed-off-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Joachim Eastwood authored
Add support for NXP's LPC18xx (Cortex-M3) and LPC43xx (Cortex-M4) SoCs. These SoCs are NXP's high preformance MCU line and can run at clock speeds up to 180 MHz for LPC18xx and 204 MHz for LPC43xx. LPC43xx is more or less a LPC18xx with a Cortex-M4F core and a few extra peripherals. The LPC43xx series also features one or two Cortex-M0 cores that can be used to offload the main M4 core. Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Reviewed-by:
Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Maxime Coquelin authored
STMicrolectronics's STM32 series is a family of Cortex-M microcontrollers. It is used in various applications, and proposes a wide range of peripherals. Tested-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- May 15, 2015
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https://github.com/rjarzmik/linuxArnd Bergmann authored
Merge "pxa changes for v4.2 cycle" from Robert Jarzmik: The main and only feature is the conversion of all pxa variants to clock framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards. This should be a disruptive cycle in the normally quiet pxa history, as the change can break any platform, and the test were performed on only 4 boards (lubbock, zylonite, mioa701, cm-x300). * tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux: ARM: pxa: Constify irq_domain_ops ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework ARM: pxa: convert eseries to clock framework ARM: pxa: Transition pxa25x and pxa27x to clk framework ARM: pxa: pxa27x skip default device initialization with DT clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc ARM: pxa: move gpio11 clock to board files ARM: pxa: change clocks init sequence
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Arnd Bergmann authored
Merge tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi into next/soc Merge "RaspberryPi SoC (mach) changes due for v4.2" from Lee Jones: * tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi: ARM: bcm2835: Move the restart/power_off handling to the WDT driver ARM: bcm2835: Drop the init_irq() hook ARM: bcm2835: Skip doing our own iotable_init() initialization
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- May 14, 2015
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Eric Anholt authored
Since the WDT is what's used to drive restart and power off, it makes more sense to keep it there, where the regs are already mapped and definitions for them provided. Note that this means you may need to add CONFIG_BCM2835_WDT to retain functionality of your kernel. Signed-off-by:
Eric Anholt <eric@anholt.net> Acked-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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Eric Anholt authored
This is the default function that gets called if the hook is NULL. Signed-off-by:
Eric Anholt <eric@anholt.net> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Tested-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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Eric Anholt authored
The only thing we were using this 16MB mapping of IO peripherals for was the uart's early debug mapping. If we just drop the map_io hook, the kernel will call debug_ll_io_init() for us, which maps the single page needed for the device. Signed-off-by:
Eric Anholt <eric@anholt.net> Tested-by:
Stephen Warren <swarren@wwwdotorg.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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Arnd Bergmann authored
Merge tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc Merge "ARM: tegra: Core SoC changes for v4.2-rc1" from Thierry Reding: A couple of changes to the core SoC support code. Perhaps the most important part is a fix for a regression in LP1 suspend/resume code that was introduced a while back. * tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: move to using a restart handler ARM: tegra20: Store CPU "resettable" status in IRAM soc/tegra: Watch wait_for_completion_timeout() return type
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- May 13, 2015
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Arnd Bergmann authored
Merge tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc Merge "SoCFPGA updates for v4.2" from Dinh Nguyen: - Add big endian support - Add earlyprintk support on UART1 that is used on Arria10 - Remove the need to map uart_io_desc - Use of_iomap to map the SCU - Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing the CPU mapping. * tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: use of_iomap to map the SCU ARM: socfpga: remove the need to map uart_io_desc ARM: socfpga: Add support for UART1 debug uart for earlyprintk ARM: socfpga: support big endian for socfpga ARM: socfpga: enable big endian for secondary core(s) ARM: debug: fix big endian operation for 8250 word mode
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Dinh Nguyen authored
Use of_iomap to map the "arm,cortex-a9-scu". By doing this, we can remove map_io in socfpga.c. Also, we can remove socfpga_smp_init_cpus, as arm_dt_init_cpu_maps is already doing the CPU mapping. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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Krzysztof Kozlowski authored
The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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Robert Jarzmik authored
Transition the PXA25x, PXA27x and PXA3xx CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files. This is the last step of clock framework transition for pxa platforms. It was tested on lubbock (pxa25x), mioa701 (pxa27x) and zylonite (pxa3xx). Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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Robert Jarzmik authored
As pxa architecture transitions to clock framework, the previously available INIT_CLKREG is no more. Use the fixed clock rate initializer to declare the "fake" CLK_CK32K in eseries. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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Robert Jarzmik authored
Transition the PXA25x and PXA27x CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files. The transition breaks the previous clocks activation of pin control (gpio11 and gpio12). Machine files should be amended to take that into account. This is the last step of clock framework transition for pxa25x and pxa27x, leaving only pxa3xx for further work. Reviewed-by:
Michael Turquette <mturquette@linaro.org> Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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Robert Jarzmik authored
When booting via DT, the default PXA devices must not have been probed before, otherwise the augmented information from the device tree is ignored. This is the twin commit of commit 82ce44d1 ("ARM: pxa3xx: skip default device initialization when booting via DT"). Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Acked-by:
Daniel Mack <daniel@zonque.org>
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Robert Jarzmik authored
Add 2 clocks which were erronously forgotten by the clock framework port, namely : - sa1100-rtc - irda for pxa2xx-ir:UARTCLK Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Acked-by:
Michael Turquette <mturquette@linaro.org>
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Robert Jarzmik authored
The pxa25x gpio11 clock output was previously selected on its pin by the clock enabling, toggling the pin function. As we transition to common clock framework, the pin function is moved to board file for the 2 users, ie. lubbock and eseries. Reviewed-by:
Michael Turquette <mturquette@linaro.org> Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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Robert Jarzmik authored
Since pxa clocks were ported to the clock framework, an ordering issue appears between clocks and clocksource initialization. As a consequence, the pxa timer clock cannot be acquired in pxa_timer, and is disabled by clock framework because it is "unused". The ordering issue is that in the kernel boot sequence : start_kernel() ... time_init() -> pxa_timer() -> here the clocksource is initialized ... rest_init() kernel_init() initcalls -> here the clocks are initialized In the current sequence, the clocks are initialized way after pxa_timer, which cannot acquire the OSTIMER0 clock. To solve this issue, the clocks initialization is moved to pxa_timer(), so that clocks are initialized before clocksource for non device-tree. For device-tree, the standard arm time_init() will take care of the ordering. Reviewed-by:
Michael Turquette <mturquette@linaro.org> Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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Arnd Bergmann authored
Merge tag 'sunxi-core-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc Merge "Allwinner core additions for 4.2" from Maxime Ripard: This pull request contains only the changes needed to support the SMP on the Allwinner A23. * tag 'sunxi-core-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: sun8i: Add SMP support for the Allwinner A23
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- May 12, 2015
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Masahiro Yamada authored
Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Masahiro Yamada authored
Initial commit for a new SoC family, UniPhier, developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation). This commit includes a minimal set of components for booting the kernel, including SMP support. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Dinh Nguyen authored
All the necessary debug uart mapping is already being done in debug_ll_io_init, there's no need for it here. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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Dinh Nguyen authored
Add support for hardware uart1 for earlyprintk support on Arria10 devkit. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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Ben Dooks authored
Now the debug and platsmp.S are fixed for big endian, the architecture can now advertise big endian support. Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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Ben Dooks authored
Update the secondary code to allow the secondary boot to work when the system is running big endian. Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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Ben Dooks authored
If the 8250 debug code is used in word mode on an big endian host then the writes need to be change into little endian for the bus. Note, we have to re-convert the value back as the debug code will inspect the value after writing it to see if a newline has been written. Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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- May 11, 2015
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Linus Torvalds authored
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git://people.freedesktop.org/~airlied/linuxLinus Torvalds authored
Pull drm fixes from Dave Airlie: "I really need to get back to sending these on my Friday, instead of my Monday morning, but nothing too amazing in here: a few amdkfd fixes, a few radeon fixes, i915 fixes, one tegra fix and one core fix" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm: Zero out invalid vblank timestamp in drm_update_vblank_count. drm/tegra: Don't use vblank_disable_immediate on incapable driver. drm/radeon: stop trying to suspend UVD sessions drm/radeon: more strictly validate the UVD codec drm/radeon: make UVD handle checking more strict drm/radeon: make VCE handle check more strict drm/radeon: fix userptr lockup drm/radeon: fix userptr BO unpin bug v3 drm/amdkfd: Initialize sdma vm when creating sdma queue drm/amdkfd: Don't report local memory size drm/amdkfd: allow unregister process with queues drm/i915: Drop PIPE-A quirk for 945GSE HP Mini drm/i915: Sink rate read should be saved in deca-kHz drm/i915/dp: there is no audio on port A drm/i915: Add missing MacBook Pro models with dual channel LVDS drm/i915: Assume dual channel LVDS if pixel clock necessitates it drm/radeon: don't setup audio on asics that don't support it drm/radeon: disable semaphores for UVD V1 (v2)
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
misc i915 fixes. * tag 'drm-intel-fixes-2015-05-08' of git://anongit.freedesktop.org/drm-intel: drm/i915: Drop PIPE-A quirk for 945GSE HP Mini drm/i915: Sink rate read should be saved in deca-kHz drm/i915/dp: there is no audio on port A drm/i915: Add missing MacBook Pro models with dual channel LVDS drm/i915: Assume dual channel LVDS if pixel clock necessitates it
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