- Jan 29, 2013
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Bryan Wu authored
This patch adds support for Tegra30 Beaver board in upstream kernel. Beaver board is a Tegra30 SoC based development board, it has following features: - T30 or T33 SoC (Qual core ARM Cortex A9) - 2 GB DDR3L - 16 GB EMMC - 1 SD slot - 1 USB Standart A port and 1 USB micro AB port - PCI-E Gig Ethernet - Audio input/output - SATA port - HDMI output - UART and JTAG Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
... and disable tri-state from the pingroup that contains the poweroff GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Bryan Wu authored
Use engineering name 'Tegra20' instead of 'Tegra2' Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
tegra30 gpio controller is not compatible with the tegra20 due to their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30 bank stride is 0x100. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed typo syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add a new evaluation board, Pluto for Tegra 114 family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add a new evaluation board, Dalmore for Tegra 114 family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The patch to add USB PHY nodes to device tree was written before Tegra supported the clocks property in device tree. Now that it does, add the required clocks properties to these nodes. This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced by clk_get(phy->dev, clock_name), as part of converting the PHY driver to a platform driver. Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Venu Byravarasu authored
Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Venu Byravarasu authored
As Tegra USB host driver is using instance number for resetting PORT0 twice, adding a new DT property for handling this. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock i2c clock information to device node. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: added second clock to 3d node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
The device tree binding models Tegra30 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: fixed typo in binding doc] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The Tegra20 CAR (Clock And Reset) Controller controls most aspects of most clocks within Tegra20. The device tree binding models this as a single monolithic clock provider, which exports many clocks. This reduces the number of nodes needed in device tree to represent these clocks. This binding is only useful for Tegra20; the set of clocks that exists on Tegra30 is sufficiently different to merit its own binding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> [pgaikwad: Added mux clk ids and sorted CAR node] Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add CPU node for Tegra30. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add CPU node for Tegra20. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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- Jan 08, 2013
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Rob Herring authored
With the addition of commit a0ae0240 (ARM: kernel: add device tree init map function), the cpu reg values must match the cpu mpidr register or we'll get warnings. For some reason, the CLUSTERID on highbank is 9, so the reg value needs to be 0x90n to quiet the warnings. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Rob Herring authored
While device_type is considered deprecated, it is still needed for tools like lshw to identify cpu nodes. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Marek Vasut authored
The second FlexCAN port uses different clock than the first one, configure correct clock to prevent hanging of the system during bringing up of the port. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Sebastian Hesselbarth authored
During merge of the mvebu patches a clock gate for pinctrl was lost. This patch just readds the clock gate. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Jan 07, 2013
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Andrew Lunn authored
The Armada XP MV78230 DT include file is missing a ; at the end of the cpu node. Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
We originally thought that the MV78230 variant of the Armada XP had four Ethernet interfaces, like the other variants MV78260 and MV78460. In fact, this is not true, and the MV78230 has only three Ethernet interfaces. So, the definitions of the Ethernet interfaces is now done as follows: * armada-370-xp.dtsi: definitions of the first two interfaces, that are common to Armada 370 and Armada XP * armada-xp.dtsi: definition of the third interface, common to all Armada XP variants. * armada-xp-mv78260.dtsi and armada-xp-mv78460.dtsi: definition of the fourth interface. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
Contrary to our understanding at the time armada-xp-mv78230.dtsi was written, the MV78230 variant of the Armada XP SoC has two cores and not one. This patch updates the .dtsi file to take into account this reality. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Andrew Lunn authored
With the change to a DT based pinctrl/gpio driver, using gpio API calls in board-*.c files no longer works, a dereferenced NULL pointer exception occurs instead. By converting the GPIO code into a fixed-regulator which gets probed later once pinctrl/gpio is available, we avoid the exception. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Stefan Peter <s.peter@mplch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Nobuhiro Iwamatsu authored
Clock Management of kirkwood has moved to DT clock providers. However, TWSI1 has not yet been done. This switches TWSI1 of 88f6282 to DT clock providers. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Andrew Lunn authored
Without the clock being held by a driver, it gets turned off at a bad time causing the SoC to lockup. This is often during reboot. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Stefan Peter <s.peter@mpl.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
The UART controller used in the Armada 370 and Armada XP SoCs is the Synopsys DesignWare 8250 (aka Synopsys DesignWare ABP UART). The improper use of the ns16550 can lead to a kernel oops during boot if a character is sent to the UART before the initialization of the driver. The DW APB has an extra interrupt that gets raised when writing to the LCR when busy. This explains why we need to use dw-apb-uart driver to handle this. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Jan 04, 2013
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Fabio Estevam authored
In the compatible field we should point the manufacturer of the board, which in this case is Buglabs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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- Jan 02, 2013
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Aaro Koskinen authored
Add DT support for twl4030_wdt. This is needed to get twl4030_wdt to probe when booting with DT. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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- Dec 29, 2012
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Kukjin Kim authored
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Kukjin Kim authored
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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- Dec 28, 2012
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Sean Paul authored
Reduce the HDMI resource size from 0x100000 to 0x70000 so it doesn't overlap the Displayport resource space. HDMI: (0x14530000 - 0x145A0000) DP: (0x145B0000 - 0x145B1000) Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Prathyush K <prathyush.k@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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- Dec 26, 2012
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Fabio Baltieri authored
Current nmk_pinctrl driver is not PRCMU dependent anymore, so it needs its own DT address resources to work properly, as done for platform_device in: f4828336 ARM: ux500: add PRCM register base for pinctrl Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- Dec 25, 2012
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Fabio Estevam authored
On the imx23-olinuxino board GPIO2_1 is connected to the LED and GPIO0_17 is the USB PHY reset. So make the IOMUX assignment properly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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- Dec 22, 2012
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Kukjin Kim authored
Commit db5b0ae0 ("Merge tag 'dt' of git://git.kernel.org/.../arm-soc" ) causes a duplicated build target. This patch fixes it and sorts out the build target alphabetically so that we can recognize something wrong easily. Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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