- Jun 17, 2013
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Brian Lilly authored
The CFA-10057 is a breakout board for the CFA-10036 that has Ethernet, USB and a 4.3" LCD screen on it. Signed-off-by: Brian Lilly <brian@crystalfontz.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Brian Lilly authored
The CFA-10055 is yet another breakout board for the CFA-10036, and is basically a CFA-10037, with the screen and LCD controller found on the CFA-10049. Signed-off-by: Brian Lilly <brian@crystalfontz.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Brian Lilly authored
The early prototypes had the chip select pin for the LCD controller wired on the GPIO 3-23, while the production run of the CFA-10049 have this chip select on the GPIO 3-5. Signed-off-by: Brian Lilly <brian@crystalfontz.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Maxime Ripard authored
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Gwenhael Goavec-Merou authored
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Marek Vasut authored
Make use of RTS/CTS lines on AUART0 and register AUART1 and AUART2 which are routed onto a pin header. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Maxime Ripard authored
The OLED display can work faster. Change the i2c controller clock frequency to remove the tearing effect that can be seen on the display. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Maxime Ripard authored
The SSD1307 was used in an early prototype that will never get distributed. The final board now has a SSD1306 instead, that has its own power generation unit and thus doesn't need any PWM. The panel attached to it also changed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Eric Bénard authored
Add auart4 2 pins configuration on SSP3 pads Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Eric Bénard authored
Add auart3 2 pins configuration on its main pads Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Eric Bénard authored
Add auart2 2 pins configuration on its main pads Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Fabio Estevam authored
MX28 has the same DIGCTL block as MX23, so adjust the compatible string to reflect that. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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- Jun 07, 2013
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Thomas Petazzoni authored
The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Jun 06, 2013
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Marc C authored
The previous mask values for the legacy ARM CPU IDs were conflicting with the CPU ID assignments for late-generation CPUs (like the Qualcomm MSM/QSD or Broadcom Brahma-15 processors). This change corrects the legacy ARM CPU ID value so that the jump table can fall-through to the appropriate cache maintenance / MMU functions. Signed-off-by: Marc C <marc.ceeeee@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Arnd Bergmann authored
In August 2012, Matthew Gretton-Dann checked a change into binutils labelled "Error on obsolete & warn on deprecated registers", apparently as part of ARMv8 support. Apparently, this was supposed to emit the message "Warning: This coprocessor register access is deprecated in ARMv8" when using certain mcr/mrc instructions and building for ARMv8. Unfortunately, the message that is actually emitted appears to be '(null)', which is less helpful in comparison. Even more unfortunately, this is biting us on every single kernel build with a new gas, because arch/arm/boot/compressed/head.S and some other files in that directory are built with -march=all since kernel commit 80cec14a "[ARM] Add -march=all to assembly file build in arch/arm/boot/compressed" back in v2.6.28. This patch reverts Russell's nice solution and instead marks the head.S file to be built for armv7-a, which fortunately lets us build all instructions in that file without warnings even on the broken binutils. Without this patch, building anything results in: arch/arm/boot/compressed/head.S: Assembler messages: arch/arm/boot/compressed/head.S:565: Warning: (null) arch/arm/boot/compressed/head.S:676: Warning: (null) arch/arm/boot/compressed/head.S:698: Warning: (null) arch/arm/boot/compressed/head.S:722: Warning: (null) arch/arm/boot/compressed/head.S:726: Warning: (null) arch/arm/boot/compressed/head.S:957: Warning: (null) arch/arm/boot/compressed/head.S:996: Warning: (null) arch/arm/boot/compressed/head.S:997: Warning: (null) arch/arm/boot/compressed/head.S:1027: Warning: (null) arch/arm/boot/compressed/head.S:1035: Warning: (null) arch/arm/boot/compressed/head.S:1046: Warning: (null) arch/arm/boot/compressed/head.S:1060: Warning: (null) arch/arm/boot/compressed/head.S:1092: Warning: (null) arch/arm/boot/compressed/head.S:1094: Warning: (null) arch/arm/boot/compressed/head.S:1095: Warning: (null) arch/arm/boot/compressed/head.S:1102: Warning: (null) arch/arm/boot/compressed/head.S:1134: Warning: (null) Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: stable@vger.kernel.org Cc: Matthew Gretton-Dann <matthew.gretton-dann@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Nicolas Pitre authored
Selecting this option produces: AS arch/arm/boot/compressed/debug.o arch/arm/boot/compressed/debug.S:4:33: fatal error: mach/debug-macro.S: No such file or directory compilation terminated. make[3]: *** [arch/arm/boot/compressed/debug.o] Error 1 The semihosting support cannot be modelled into a senduart macro as it requires memory space for argument passing. So the CONFIG_DEBUG_LL_INCLUDE may not have any sensible value and the include directive should be omitted. While at it, let's add proper semihosting output support to the decompressor. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- Jun 03, 2013
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Suman Anna authored
OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM. The PWM capability property is missing from the node definitions of couple of timers. Add ti,timer-pwm attribute for timer 5, 6, 8 and 11. Signed-off-by: Suman Anna <s-anna@ti.com> [benoit.cousson@linaro.org: Update changelog and subject to highlight the fix] Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
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Kevin Hilman authored
Earlier commits ensured proper muxing of pins related to proper TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM: OMAP4: TWL: mux sys_drm_msecure as output for PMIC). However these only fixed legacy boot and not DT boot. For DT boot, the default mux values need to be set properly in DT. Special thanks to Nishanth Menon for the review and catching some major flaws in earlier versions. Tested on OMAP4430/Panda and OMAP4460/Panda-ES. Cc: Nishanth Menon <nm@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> [benoit.cousson@linaro.org: Slightly change the subject to align board name with file name] Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
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Lars Poeschel authored
The gpmc driver is actually looking for "gpmc,num-cs" and "gpmc,num-waitpins" properties in DT. The binding doc also states this. Correct the properties in the dts to provide the right values for the gpmc driver. Signed-off-by: Lars Poeschel <poeschel@lemonage.de> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
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Jongsung Kim authored
Stephen Warren reported the recent commit 78506f22 (add support for extended FIFO-size of PL011-r1p5) breaks the serial port on the BCM2835 ARM SoC. A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs. The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for this compatibility issue, this patch overrides the HW UART periphid register values with the actually compatible UART periphid 0x00241011 (r1p3 or r1p4). Reported-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jongsung Kim <neidhard.kim@lge.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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- May 24, 2013
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Boris BREZILLON authored
The PA24 pin is wrongly assigned to peripheral B. In the current config there is 2 ETX3 pins (PA11 and PA24) and no ETXER pin (PA22). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: stable <stable@vger.kernel.org> # 3.8+
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Jonas Andersson authored
The CSPI controller has only one clock, but the driver spi-imx.c needs clock "per" to calculate bitrate divisor. Signed-off-by: Jonas Andersson <jonas@microbit.se> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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- May 21, 2013
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Linus Walleij authored
The assignment of IRQ for the SMC91x ethernet adapter had two problems making it non-working: - It was not put into the ethernet device node. Let's do this by using the board-specific overlay, so we can make other overlays on other Nomadik boards. - The IRQ number was actually completely wrong, this was the number for NHK8815, not S8815. After this ethernet starts working on the USB S8815. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Gregory CLEMENT authored
During the conversion to the internal-regs' subnode, the L2-cache node haven not been converted (due to a wrong choice made by myself during the resolution of the merge conflict when I rebased the commit). This leads to wrong address for L2 cache which prevent it to be used on Armada 370. This commit fix the address reg of the e L2-cache node. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Vivek Gautam authored
Adding usbphy node for Exynos5250 along with the necessary device data to be parsed. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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- May 20, 2013
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Thomas Petazzoni authored
Since 82a68267 ('ARM: dts: mvebu: Convert all the mvebu files to use the range property') all the device nodes of Armada 370/XP are under a common 'ranges' property that translates the device register addresses into their absolute address, thanks to the base address of the internal register space. However, beyond just the register areas, there are also PCIe I/O and memory regions, whose addresses should be properly translated. This patch fixes the Armada 370 and XP ranges property to take PCIe into account properly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- May 18, 2013
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Ezequiel Garcia authored
With the latest device tree reorganization which introduced the 'internal-reg' node, now the only region translated is the internal register's. This makes the description of the hardware incomplete, for it lacks the Device Bus childs address space. In order to fix this, it's required to add a 'ranges' entry with a suitable address space to map Device Bus childs, on a per-board basis. This patch fixes the ranges property on the Armada XP GP board. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- May 16, 2013
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Tony Lindgren authored
Commit ad871c10 (ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards) added support for MUSB on omap3 for device tree, but added the interrupts the wrong way probably as they were copied from the omap4.dtsi file. On omap3 we have TI specific interrupt controller, not GIC. Fix this by specifying the interrupt following the TI INTC binding. Without this fix MUSB won't work as it is trying to use irq0 instead of irq92. Signed-off-by: Tony Lindgren <tony@atomide.com>
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- May 14, 2013
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Ludovic Desroches authored
Instead of requesting all available spi cs-gpios, request only the ones used on the board, in our case on the cpu module. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Nicolas Ferre authored
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: stable <stable@vger.kernel.org> # 3.8+
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Ezequiel Garcia authored
With the latest device tree reorganization which introduced the 'internal-reg' node, now the only region translated is the internal register's. This makes the description of the hardware incomplete, for it lacks the Device Bus childs address space. In order to fix this, it's required to add a 'ranges' entry with a suitable address space to map Device Bus childs, on a per-board basis. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- May 13, 2013
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Thomas Petazzoni authored
The mpic alias is already defined in the common armada-370-xp.dtsi, so there's no need to repeat it at the armada-xp.dtsi and armada-370.dtsi level. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Maxime Ripard authored
Commit b00adbe0 ("ARM: sunxi: Rename uart nodes to serial") changed the node names in the DTSI, changes that were not accordingly made to the Mini X-Plus device tree. This breakage slipped through because it was not properly declared in the Makefile. Fix both issues. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- May 10, 2013
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Doug Anderson authored
The 'samsung,vbus-gpio' was submitted before pinmux landed for exynos5250 and uses the old-style gpio specifier. Fix the two exynos5250 boards that use it. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Trivial patch, adding the i2c Cypress trackpad used on Snow. Signed-off-by: Olof Johansson <olof@lixom.net> Reviewed-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com>
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Jason Cooper authored
If a board isn't using twl4030, then dtc will complain about the missing phandle (which is in twl4030.dtsi). Move the phy declaration to the dts files. Signed-off-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
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- May 09, 2013
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Tony Lindgren authored
The bootloader configures the pins, but has pull bits set without pull enable bits. While this is harmless, and won't do anything, it seems to cause confusion at least for me every time looking at the pin configuration. Fix it for DT based boot. Signed-off-by: Tony Lindgren <tony@atomide.com>
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Philip Avinash authored
Add GPMC data node to AM33XX device tree file. Signed-off-by: Philip Avinash <avinashphilip@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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