- Jun 20, 2018
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Viresh Kumar authored
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Vicente Bergas authored
Everything is in place and working, it only needed to be wired up. Signed-off-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jun 17, 2018
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Klaus Goger authored
Update all 64bit rockchip devicetree files to use SPDX-License-Identifiers. All devicetrees claim to be either GPL or X11 while the actual license text is MIT. Therefore we use MIT for the SPDX tag as X11 is clearly wrong. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Brian Norris <briannorris@chromium.org> Acked-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Apr 16, 2018
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Jeffy Chen authored
Add clocks in iommu nodes, since we are going to control clocks in rockchip iommu driver. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enric Balletbo i Serra authored
Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Lin Huang authored
These clocks do not assign default clock frequency, and use the default cru register value to get frequency, so if cpll increase frequency, these clocks also increase their frequency, that may exceed their signed off frequency. So assign default clock for them to avoid it. NOTE: on none of the boards currently in mainline do we expect CPLL to be anything other than 800 MHz, but some future boards might have it. It's still good to be explicit about the clock rates to make diffing against future boards easier and also to rely less on BIOS muxing. Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Mar 12, 2018
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Shunqian Zheng authored
The ACLK_VIO is a parent clock used by a several children, its suggested clock rate is 400MHz. Right now it gets 400MHz because it sources from CPLL(800M) and divides by 2 after reset. It's good not to rely on default values like this, so let's explicitly set it. NOTE: it's expected that at least one board may override cru node and set the CPLL to 1.6 GHz. On that board it will be very important to be explicit about aclk-vio being 400 MHz. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Mar 02, 2018
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Heiko Stuebner authored
This reverts commit c301b327 . While this works splendidly on rk3399-gru devices using the cros-ec extcon, other rk3399-based devices using the fusb302 or no power-delivery controller at all don't probe at all anymore, as the typec-phy currently always expects the extcon to be available and therefore defers probing indefinitly on these. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Feb 14, 2018
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Chris Zhong authored
Add a node for the cdn DP controller which is embedded in the rk3399 SoC. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [fixed whitespaces instead of tabs, dropped unnecessary address+size-cells and fixed the number of interrupt cells] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Feb 12, 2018
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Klaus Goger authored
Add pin definition for I2S0 if used as a 2-channel only bus. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shunqian Zheng authored
There are three pins can act as cif test clock for rk3399. They're sourced from 24M and output 24M by default and some boards may use them as camera 24M xvclk. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Yakir Yang authored
The pclk_vio_grf supply power for VIO GRF IOs, if it is disabled, driver would failed to operate the VIO GRF registers. The clock is optional but one of the side effects of don't have this clk is that the Samsung Chromebook Plus fails to recover display after a suspend/resume with following errors: rockchip-dp ff970000.edp: Input stream clock not detected. rockchip-dp ff970000.edp: Timeout of video streamclk ok rockchip-dp ff970000.edp: unable to config video Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [this should also fix display failures when building rockchip-drm as module] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Dec 17, 2017
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Enric Balletbo i Serra authored
Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enric Balletbo i Serra authored
After commit '06c47e62 usb: dwc3: of-simple: Add support to get resets for the device' you can add the reset property to the dwc3 node, the reset is required for the controller to work properly, otherwise bind / unbind stress testing of the USB controller on rk3399 we'd often end up with lots of failures that looked like this: phy phy-ff800000.phy.9: phy poweron failed --> -110 dwc3 fe900000.dwc3: failed to initialize core dwc3: probe of fe900000.dwc3 failed with error -110 Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enric Balletbo i Serra authored
The aclk_usb3 must be enabled to support USB3 for rk3399. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enric Balletbo i Serra authored
Add the usb3 power-domain, its qos area and assign it to the usb device node. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Dec 04, 2017
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Nickey Yang authored
We might include additional ports in derivative device trees, so the 'port' node should have an address, and the parent 'ports' node needs /#{addres,size}-cells. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Nickey Yang authored
This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
We've documented this one already, but we didn't add it to the DTSI yet. Suggested-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Oct 18, 2017
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Jacob Chen authored
This patch add the RGA dt config of RK3399 SoC. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Oct 15, 2017
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Pierre-Hugues Husson authored
Add the HDMI CEC controller main clock coming from the CRU. Signed-off-by: Pierre-Hugues Husson <phh@phh.me> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Sep 26, 2017
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Nickey Yang authored
The clk of grf must be enabled before writing grf register for rk3399. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> [the grf clock is already part of the binding since march 2017] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Sep 20, 2017
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Nickey Yang authored
There is a further gate in between the mipidphy reference clock and the actual ref-clock input to the dsi host, making the clock hirarchy look like clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll Fix the clock reference so that the whole clock subtree gets enabled when the dsi host needs it. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> [amended commit message] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 30, 2017
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Shawn Lin authored
Convert all RK3399 platforms to use per-lane PHY model in order to save more power by idling unused lane(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
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- Aug 22, 2017
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Simon Xue authored
Add VPU/VDEC/IEP/ISP0/ISP1 iommu nodes Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 19, 2017
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Kever Yang authored
We need to init vop aclk and hclk incase the U-Boot does not do the initialize. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 18, 2017
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William Wu authored
RK3399 USB DWC3 controller has a issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. It's because that the inter-packet delay between the SSPLIT token to SETUP token is about 566ns, more then the USB spec requirement. This patch adds a quirk "snps,dis-tx-ipgap-linecheck-quirk" to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 06, 2017
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Jacob Chen authored
Add an hdmi node, and also add hdmi endpoints to vopb and vopl output port nodes. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Jacob Chen authored
Add an mipi node, and also add mipi endpoints to vopb and vopl output port nodes. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Yakir Yang authored
Add an edp node, and also add edp endpoints to vopb and vopl output port nodes. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Elaine Zhang authored
1. add pd node for RK3399 Soc 2. create power domain tree 3. add qos node for domain Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Mark Yao authored
Add devicetree nodes for rk3399 VOP (Video Output Processors), and the top level display-subsystem root node. Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the VOPs' output ports. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 01, 2017
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Caesar Wang authored
This patch updates the dynamic-power-coefficient for big cluster on rk3399 SoCs. The dynamic power consumption of the CPU is proportional to the square of the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f Where Voltage is in uV, frequency is in MHz. As the following is the tested data on rk3399's big cluster. frequency(MHz) Voltage(V) Current(mA) Dynamic-power-coefficient 24 0.8 15 48 0.8 23 ~417 96 0.8 40 ~443 216 0.8 82 ~438 312 0.8 115 ~430 408 0.8 150 ~455 So the dynamic-power-coefficient average value is about 436. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jul 23, 2017
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Shawn Lin authored
Kill these two pinctrl reference totally from rk3399 as it never work indeed. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Caesar Wang authored
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq opp table. RK3399 and RK3399-OP1 SoCs have a different recommendation table with gpu opp. Also, the ARM's mali driver found on https://developer.arm.com/products/software/mali-drivers/midgard-kernel . Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jul 16, 2017
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Caesar Wang authored
The SdioAudio power domain includes the i2s/spdif/spi5/sdio. So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order to save more power consumption. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
Provide the dynamic power coefficient of the big and little CPU clusters. These numbers are currently in use on the Samsung Chromebook Plus ("Kevin"). The power allocator thermal governor doesn't know how to do anything if it doesn't get power parameters from its cooling devices (in this case, CPUfreq). So this effectively enables the power-allocator governor. Signed-off-by: Brian Norris <briannorris@chromium.org> [set the property in each core node] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Klaus Goger authored
replace all occurrences of sdmcc with sdmmc in the arm64 rockchip devicetree files. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- May 30, 2017
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Heiko Stuebner authored
This is used by bootloaders to override the mac address in the devicetree if needed. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- May 23, 2017
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Shawn Lin authored
Make full use of 32 regions and increase IORESOURCE_MEM_64 so that we could have more chance to support PCIe switch with more endpoints attached to our RC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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