- Sep 14, 2016
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Jamie Lentin authored
This is a router based on the mv88f5181 chipset. http://www.netgear.com/support/product/WNR854T.aspx http://wiki.openwrt.org/toh/netgear/wnr854t [gregory.clement@free-electrons.com: - extract dt part from "arm: orion5x: Add DT-based support for Netgear WNR854T" - squashed "arm: orion5x: Alias uart0 to serial0 for all orion5x" into this commit and move serial0 alias from dtsi to dts] Signed-off-by:
Jamie Lentin <jm@lentin.co.uk> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Jamie Lentin authored
Common definitions for the SoC for board definitions to use. [gregory.clement@free-electrons.com: fix commit title] Signed-off-by:
Jamie Lentin <jm@lentin.co.uk> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Jamie Lentin authored
orion-wdt refuses to start without these properties defined, so lift definitions out of kirkwood/dove.dtsi [gregory.clement@free-electrons.com: fix commit title] Signed-off-by:
Jamie Lentin <jm@lentin.co.uk> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Aug 29, 2016
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Arnd Bergmann authored
The SPI controller in the arch/arm/boot/dts/armada-39x.dtsi file has moved to a different location in the hierarchy, which breaks the overrides in the board specific file: Warning (reg_format): "reg" property in /soc/internal-regs/spi@10680/spi-flash@1 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /soc/internal-regs/spi@10680/spi-flash@1 This changes the board to reference the spi controller by its label (which has not changed) rather than the full path. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Fixes: 0160a4b6 ("ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node") Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Aug 26, 2016
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Chris Packham authored
Add pin control information for the NAND flash interface. This interface is multiplexed with the device bus interface to the function is "dev" not "nand" as one might expect. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Jason Cooper authored
By assigning the pin hog to the pinctrl node, we correctly configure the MPPs. However, they are not available to userspace. Fix this by assigning the hogs to the gpio node. After this, the following works as expected: # echo 28 >/sys/class/gpio/export # echo low >/sys/class/gpio/gpio28/direction [gregory.clement@free-electrons.com: fix title] Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Aug 08, 2016
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Grzegorz Jaszczyk authored
This commit adds description for the following features for this board: - Serial port - PCIe interfaces - USB2.0 - USB3.0 - SDIO - 1024 MiB NAND-FLASH - SATA - I2C buses Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
This commit adds description for following features for this board: - Serial port - I2C buses - 16MB SPI-NOR - USB2.0 - USB3.0 - PCIe interfaces Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The Marvell Armada 398 Development board contains both USB2.0 and USB3.0 ports, which can be handled by existing drivers. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
Beside interfaces described in the armada-39x.dtsi and armada-395.dtsi, the Armada 398 SoC family supports 2 additional SATA port (2 ports in one unit) Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
Beside interfaces described in the armada-39x.dtsi, the Armada 395 SoC family supports: 2 x SATA3 (2 ports in one unit) and the USB3.0 Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
Despite that FS states that rtc is present only in A395 and A398 and not in A390, the rtc is working with A390. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The whole Armada 39x SoC family of processors has GPIO's which all can be supported with existing driver. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The whole Armada 39x SoC family of processors has watchdog which can be supported with existing driver. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by:
Lior Amsalem <alior@marvell.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The whole Armada 39x SoC family of processors has thermal sensor which can be supported with existing driver. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
This commit enables: - CA9's Performance Monitor Unit - CA9 MPcore SoC Controller - Coherency fabric on Armada 39x, basing on the Armada 38x (which has the same CA9 CPU). Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by:
Lior Amsalem <alior@marvell.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
Commit 1140011e ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") has extended the Device Tree binding used to describe PXAv3 SDHCI controllers in order to be able to use the SDR50 and DDR50 modes. This commit updates the Device Tree description of the Armada 39x SDHCI controller in other to take advantage of this functionality. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The armada-390.dtsi was broken since the first patch which adds Device Tree files for Armada 39x SoC was introduced. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: <stable@vger.kernel.org> # 4.0+ Fixes 538da83d ("ARM: mvebu: add Device Tree files for Armada 39x SoC and board") Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The Armada 385 Access Point Development board contains NAND FLSH which is already enabled in existing dts. Nevertheless the default partition description was missing. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The Armada 385 Access Point Development board contains USB port, which can be handled by existing orion-ehci driver. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Stefan Roese authored
This patch adds the static MBus mappings for all supported SPI devices (8 per controller) for the direct access SPI mode. They can be configured and enabled by setting these MBus mapping in the 'ranges' property of the per-board 'soc' node. If nothing is changed here, the default 'normal' (indirect) SPI mode is used. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Mark Brown <broonie@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Stefan Roese authored
This patch moves all Armada 370/XP/38x/39x SPI controller nodes from the 'internal-regs' node down into the 'soc' node. This is in preparation to enable the usage of the SPI direct access mode. A follow-up patch will add the static MBus mappings for the SPI devices into the 'reg' property of the SPI controller DT node. By moving these SPI controller nodes, this patch also makes use of the labels rather than keeping the tree structure. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Mark Brown <broonie@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Stefan Roese authored
This patch defines and uses common Armada XP pinctrl settings in armada-xp.dtsi for the SPI1 interface (MPP13,14,16,17). Signed-off-by:
Stefan Roese <sr@denx.de> Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Aug 03, 2016
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Vitaly Andrianov authored
This commit adds definition for cpu_on, cpu_off and cpu_suspend commands. These definitions must match the corresponding PSCI definitions in boot monitor. Having those command and corresponding PSCI support in boot monitor allows run time CPU hot plugin. Link: http://lkml.kernel.org/r/E1b8koV-0004Hf-2j@rmk-PC.armlinux.org.uk Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Vitaly Andrianov <vitalya@ti.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk> Cc: Pratyush Anand <panand@redhat.com> Cc: Eric Biederman <ebiederm@xmission.com> Cc: Dave Young <dyoung@redhat.com> Cc: Baoquan He <bhe@redhat.com> Cc: Vivek Goyal <vgoyal@redhat.com> Cc: Simon Horman <horms@verge.net.au> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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- Jul 23, 2016
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Stefan Agner authored
Replace the non-standard vendor prefix stm with st for STMicroelectronics. The drivers do not specify the vendor prefixes since the I2C Core strips them away from the DT provided compatible string. Therefore, changing existing device trees does not have any impact on device detection. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Rob Herring <robh@kernel.org>
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- Jul 18, 2016
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Hans de Goede authored
The inet86dz board is a board used in 7" tablets from various oems. These tablets are a23 based 7" tablets featuring a 1024x600 LCD, 512MB RAM, 4G NAND, rtl8188etv usb wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
The Polaroid MID2407PXE03 is an a23 based 7" tablet based on a M86_MB V2.0 PCB, featuring a 800x480 LCD, 512MB RAM, 4G NAND, esp8089 wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
This results in quite a nice cleanup for this dts file. As an added bonus this also enables backlight, regulator and full otg support. I've tested that all these works as advertised. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
This results in quite a nice cleanup for this dts file. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
Add a drivevbus-supply property so that the drivevbus regulator reports the right voltage value. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
Copy sun8i-q8-common.dtsi to sun8i-reference-design-tablet.dtsi. This is part of renaming all the sun?i-q8-common.dtsi files to sun?i-reference-design-tablet.dtsi since most of the hw-config in there is shared by all sunxi tablets. Note that in this case we keep sun5i-q8-common.dtsi as it is shared between a23 / a33 q8 tablets. Also we leave the usb-wifi config in there (rather then in sun8i-reference-design-tablet.dtsi) as most sun8i tablets use sdio wifi rather then usb wifi. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
This results in a nice cleanup for this dts file. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
This results in quite a nice cleanup for this dts file. Note as a side-effect this also enables the on board speaker / headphones out. I've tested that this works as advertised. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
Remove all mention of q8 from sun5i-reference-design-tablet.dtsi. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
Set lradc vref to the actual avcc ldo, rather then to the fixed 3v0 regulator from common-regulators.dtsi. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
Rename sun5i-q8-common.dtsi to sun5i-reference-design-tablet.dtsi. This is part of renaming all the sun?i-q8-common.dtsi files to sun?i-reference-design-tablet.dtsi since most of the hw-config in there is shared by all sunxi tablets. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
This is a preparation patch for renaming sun5i-q8-common.dtsi to sun5i-reference-design-tablet.dtsi and sharing it between all the A13 tablet dts files. Since we only have a panel config for the 18 tablets (for now) move this to the q8 specific dts file. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Hans de Goede authored
Rename sunxi-q8-common.dtsi to sunxi-reference-design-tablet.dtsi. This is part of renaming all the sun?i-q8-common.dtsi files to sun?i-reference-design-tablet.dtsi since most of the hw-config in there is shared by all sunxi tablets. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Matthew McClintock authored
Commit 0dfd582e ("watchdog: qcom: use timer devicetree binding") moved to use the watchdog as a subset timer register block. Some devices have the watchdog completely standalone with slightly different register offsets as well so let's account for the differences here. The existing "kpss-standalone" compatible string doesn't make it entirely clear exactly what the device is so rename to "kpss-wdt" to reflect watchdog timer functionality. Also update ipq4019 DTS with an SoC specific compatible. Signed-off-by:
Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by:
Thomas Pedersen <twp@codeaurora.org> Reviewed-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Wim Van Sebroeck <wim@iguana.be>
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Matthew McClintock authored
Update the compatible string to align with driver and also add SoC specific string to DTS. CC: linux-watchdog@vger.kernel.org Signed-off-by:
Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by:
Thomas Pedersen <twp@codeaurora.org> Reviewed-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Wim Van Sebroeck <wim@iguana.be>
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