- Sep 14, 2016
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Jamie Lentin authored
This is a router based on the mv88f5181 chipset. http://www.netgear.com/support/product/WNR854T.aspx http://wiki.openwrt.org/toh/netgear/wnr854t [gregory.clement@free-electrons.com: - extract dt part from "arm: orion5x: Add DT-based support for Netgear WNR854T" - squashed "arm: orion5x: Alias uart0 to serial0 for all orion5x" into this commit and move serial0 alias from dtsi to dts] Signed-off-by:
Jamie Lentin <jm@lentin.co.uk> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Jamie Lentin authored
Common definitions for the SoC for board definitions to use. [gregory.clement@free-electrons.com: fix commit title] Signed-off-by:
Jamie Lentin <jm@lentin.co.uk> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Jamie Lentin authored
orion-wdt refuses to start without these properties defined, so lift definitions out of kirkwood/dove.dtsi [gregory.clement@free-electrons.com: fix commit title] Signed-off-by:
Jamie Lentin <jm@lentin.co.uk> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Aug 29, 2016
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Arnd Bergmann authored
The SPI controller in the arch/arm/boot/dts/armada-39x.dtsi file has moved to a different location in the hierarchy, which breaks the overrides in the board specific file: Warning (reg_format): "reg" property in /soc/internal-regs/spi@10680/spi-flash@1 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /soc/internal-regs/spi@10680/spi-flash@1 This changes the board to reference the spi controller by its label (which has not changed) rather than the full path. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Fixes: 0160a4b6 ("ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node") Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Aug 26, 2016
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Chris Packham authored
Add pin control information for the NAND flash interface. This interface is multiplexed with the device bus interface to the function is "dev" not "nand" as one might expect. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Jason Cooper authored
By assigning the pin hog to the pinctrl node, we correctly configure the MPPs. However, they are not available to userspace. Fix this by assigning the hogs to the gpio node. After this, the following works as expected: # echo 28 >/sys/class/gpio/export # echo low >/sys/class/gpio/gpio28/direction [gregory.clement@free-electrons.com: fix title] Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Aug 08, 2016
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Grzegorz Jaszczyk authored
This commit adds description for the following features for this board: - Serial port - PCIe interfaces - USB2.0 - USB3.0 - SDIO - 1024 MiB NAND-FLASH - SATA - I2C buses Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
This commit adds description for following features for this board: - Serial port - I2C buses - 16MB SPI-NOR - USB2.0 - USB3.0 - PCIe interfaces Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The Marvell Armada 398 Development board contains both USB2.0 and USB3.0 ports, which can be handled by existing drivers. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
Beside interfaces described in the armada-39x.dtsi and armada-395.dtsi, the Armada 398 SoC family supports 2 additional SATA port (2 ports in one unit) Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
Beside interfaces described in the armada-39x.dtsi, the Armada 395 SoC family supports: 2 x SATA3 (2 ports in one unit) and the USB3.0 Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
Despite that FS states that rtc is present only in A395 and A398 and not in A390, the rtc is working with A390. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The whole Armada 39x SoC family of processors has GPIO's which all can be supported with existing driver. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The whole Armada 39x SoC family of processors has watchdog which can be supported with existing driver. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by:
Lior Amsalem <alior@marvell.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The whole Armada 39x SoC family of processors has thermal sensor which can be supported with existing driver. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
This commit enables: - CA9's Performance Monitor Unit - CA9 MPcore SoC Controller - Coherency fabric on Armada 39x, basing on the Armada 38x (which has the same CA9 CPU). Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by:
Lior Amsalem <alior@marvell.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
Commit 1140011e ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") has extended the Device Tree binding used to describe PXAv3 SDHCI controllers in order to be able to use the SDR50 and DDR50 modes. This commit updates the Device Tree description of the Armada 39x SDHCI controller in other to take advantage of this functionality. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The armada-390.dtsi was broken since the first patch which adds Device Tree files for Armada 39x SoC was introduced. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: <stable@vger.kernel.org> # 4.0+ Fixes 538da83d ("ARM: mvebu: add Device Tree files for Armada 39x SoC and board") Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The Armada 385 Access Point Development board contains NAND FLSH which is already enabled in existing dts. Nevertheless the default partition description was missing. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Grzegorz Jaszczyk authored
The Armada 385 Access Point Development board contains USB port, which can be handled by existing orion-ehci driver. Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Stefan Roese authored
This patch adds the static MBus mappings for all supported SPI devices (8 per controller) for the direct access SPI mode. They can be configured and enabled by setting these MBus mapping in the 'ranges' property of the per-board 'soc' node. If nothing is changed here, the default 'normal' (indirect) SPI mode is used. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Mark Brown <broonie@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Stefan Roese authored
This patch moves all Armada 370/XP/38x/39x SPI controller nodes from the 'internal-regs' node down into the 'soc' node. This is in preparation to enable the usage of the SPI direct access mode. A follow-up patch will add the static MBus mappings for the SPI devices into the 'reg' property of the SPI controller DT node. By moving these SPI controller nodes, this patch also makes use of the labels rather than keeping the tree structure. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Mark Brown <broonie@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Stefan Roese authored
This patch defines and uses common Armada XP pinctrl settings in armada-xp.dtsi for the SPI1 interface (MPP13,14,16,17). Signed-off-by:
Stefan Roese <sr@denx.de> Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Aug 05, 2016
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Rich Felker authored
Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
This defconfig is intended not to be specific to a particular board; it enables drivers for all currently-supported hardware, and should be updated to include additional drivers as they are added. Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
Enable common clk framework for DT-based boards and disable code that depends on the legacy sh clk framework when common clk is enabled. Once legacy drivers are converted over, the old code can be removed entirely. Signed-off-by:
Rich Felker <dalias@libc.org>
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Yoshinori Sato authored
Signed-off-by:
Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by:
Rich Felker <dalias@libc.org>
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Markus Elfring authored
The mempool_destroy() function tests whether its argument is NULL and then returns immediately. Thus the test around the calls is not needed. This issue was detected by using the Coccinelle software. Signed-off-by:
Markus Elfring <elfring@users.sourceforge.net> Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
Support is hooked up via a cpu start method specified in the device tree, and also depends on DT nodes that describe the interfaces for performing IPI and identifying which cpu execution is taking place on. The currently used method is a form of spin table, where secondary cpus are unblocked by writing to a special address. Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
The SH2 version of entry.S uses global variables, which need to be cpu-local in order to work with SMP. For ease of access from asm, simply use arrays indexed by cpu number, and require the availability of an address (mmio register or properly setup per-cpu memory) from which the current cpu's index can be read. Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
The version of futex.h in asm-generic should really be adapted to do the same thing so that this hideous code does not have to be duplicated per-arch. Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
The J-Core cpu has, as an ISA extension, an atomic compare-and-swap instruction cas.l which applications need to use (instead the imask or gusa atomic models, which are fundamentally limited to UP) for synchronization in order to be compatible with SMP systems. Provide a hwcap flag so that it's possible to do runtime selection and support both. Signed-off-by:
Rich Felker <dalias@libc.org>
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Rich Felker authored
At the CPU/ISA level, the J2 is compatible with SH-2, and thus the changes to add J2 support build on existing SH-2 support. However, J2 does not duplicate the memory-mapped SH-2 features like the cache interface. Instead, the cache interfaces is described in the device tree, and new code is added to be able to access the flat device tree at early boot before it is unflattened. Support is also added for receiving interrupts on trap numbers in the range 16 to 31, since the J-Core aic1 interrupt controller generates these traps. This range was unused but nominally for hardware exceptions on SH-2, and a few values in this range were used for exceptions on SH-2A, but SH-2A has its own version of the relevant code. No individual cpu subtypes are added for J2 since the intent moving forward is to represent SoCs with device tree rather than as hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item exists only to fit into the existing cpu selection mechanism until it is overhauled. Signed-off-by:
Rich Felker <dalias@libc.org>
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Dan Carpenter authored
We should set the error code here rather than incorrectly returning 0. Otherwise static checkers complain. Link: http://lkml.kernel.org/r/20160804053525.GM775@mwanda Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Alexandre Bounine <alexandre.bounine@idt.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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James Hogan authored
The LNKGET based atomic sequence in __cmpxchg_u32 has slightly incorrect constraints for the return value which under certain circumstances can allow an address unit register to be used as the first operand of a CMP instruction. This isn't a valid instruction however as the encodings only allow a data unit to be specified. This would result in an assembler error like the following: Error: failed to assemble instruction: "CMP A0.2,D0Ar6" Fix by changing the constraint from "=&da" (assigned, early clobbered, data or address unit register) to "=&d" (data unit register only). The constraint for the second operand, "bd" (an op2 register where op1 is a data unit register and the instruction supports O2R) is already correct assuming the first operand is a data unit register. Other cases of CMP in inline asm have had their constraints checked, and appear to all be fine. Fixes: 6006c0d8 ("metag: Atomics, locks and bitops") Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-metag@vger.kernel.org Cc: <stable@vger.kernel.org> # 3.9.x-
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- Aug 04, 2016
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Jason Baron authored
The jump table can reference text found in an __exit section. Thus, instead of discarding it at build time, include EXIT_TEXT as part of __init and it will be released when the system boots. Link: http://lkml.kernel.org/r/60284113bb759121e8ae3e99af1535647e52123f.1467837322.git.jbaron@akamai.com Signed-off-by:
Jason Baron <jbaron@akamai.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "David S. Miller" <davem@davemloft.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Chris Metcalf <cmetcalf@mellanox.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Joe Perches <joe@perches.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Chris Metcalf authored
Previously, all the __exit sections were just dropped by the link phase. However, if there are static_key (jump label) constructs in __exit sections that are not modules, the link fails with the message: `.exit.text' referenced in section `__jump_table' of xxx.o: defined in discarded section `.exit.text' of xxx.o Support this usage by keeping the .exit.text sections in the final image if JUMP_LABEL is defined, then discarding them once initialization is complete. Link: http://lkml.kernel.org/r/bfd7c107c610c30e992868ebfe2a5d796a097464.1467837322.git.jbaron@akamai.com Signed-off-by:
Jason Baron <jbaron@akamai.com> Signed-off-by:
Chris Metcalf <cmetcalf@mellanox.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Joe Perches <joe@perches.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Jason Baron authored
The jump table can reference text found in an __exit section. Thus, instead of discarding it at build/link time, include EXIT_TEXT as part of __init and release it at system boot time. Without this patch the link fails with: `.exit.text' referenced in section `__jump_table' of xxx.o: defined in discarded section `.exit.text' of xxx.o Link: http://lkml.kernel.org/r/d822da427ab07a02a394602eca687104ff682f83.1467837322.git.jbaron@akamai.com Signed-off-by:
Jason Baron <jbaron@akamai.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Chris Metcalf <cmetcalf@mellanox.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Joe Perches <joe@perches.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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