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    • Phil Elwell's avatar
      ARM: proc-v7: Retry uncached stmia if necessary · 3e1698ed
      Phil Elwell authored
      A failure of some CPU cores to come online has been traced to the
      failure of a stm instruction while the cache is disabled. The symptom
      is that the saved values read back as zeroes, a catastrophic error since
      one of the values is a return address.
      
      This patch forces a readback and retry until the correct value is
      returned,
      
      Notes:
      
      At this stage in the boot process the core is running with its cache
      disabled. Before enabling the cache its contents must be explicitly
      invalidated, a process that requires quite a few registers that the
      caller must preserve. Evidence suggests that something is writing a
      block of zeroes over that space at a time when all other cores should
      be idle, possibly some kind of write-combiner, and retrying is an
      attempt to avoid the problem.
      
      The previous attempted fix (forcing the accesses to only be 4-byte
      aligned) appears to have only worked for a while and likely for less
      obvious reasons such as a change in code alignment.
      
      See: https://github.com/Hexxeh/rpi-firmware/issues/232
      
      
      
      Signed-off-by: default avatarPhil Elwell <phil@raspberrypi.com>
      3e1698ed
    • Phil Elwell's avatar
      Revert "ARM: proc-v7: Force misalignment of early stmia" · 36d449a9
      Phil Elwell authored
      This reverts commit fe4cc0ed
      
      .
      
      The speculative patch that this commit reverts is proving to not be
      effective any more, so revert it and try a new approach.
      
      Signed-off-by: default avatarPhil Elwell <phil@raspberrypi.com>
      36d449a9
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