- Jan 29, 2013
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Hiroshi Doyu authored
Add a new evaluation board, Dalmore for Tegra 114 family. Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add tegra_chip_id TEGRA114 0x35 Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by:
Joseph Lo <josephl@nvidia.com> Acked-by:
Colin Cross <ccross@android.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes. For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The patch to add USB PHY nodes to device tree was written before Tegra supported the clocks property in device tree. Now that it does, add the required clocks properties to these nodes. This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced by clk_get(phy->dev, clock_name), as part of converting the PHY driver to a platform driver. Acked-by:
Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Venu Byravarasu authored
Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by:
Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Venu Byravarasu authored
As Tegra USB host driver is using instance number for resetting PORT0 twice, adding a new DT property for handling this. Signed-off-by:
Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by:
Alan Stern <stern@rowland.harvard.edu> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Venu Byravarasu authored
USB register base address and sizes defined in iomap.h are not used in any files other than board-dt-tegra20.c. Hence removed those defines from header file and using the absolute values in board files. Signed-off-by:
Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Remove AUXDATA as clocks are initialized from device node. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Remove AUXDATA as clock are initialized from device node. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock i2c clock information to device node. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock information to device nodes. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: added second clock to 3d node] Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add clock information to device nodes. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Remove all legacy clock code from mach-tegra. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Migrate Tegra clock support to drivers/clk/tegra, this involves moving: 1. definition of tegra_cpu_car_ops to clk.c 2. definition of reset functions to clk-peripheral.c 3. change parent of cpu clock. 4. Remove legacy clock initialization. 5. Initialize clocks using DT. 6. Remove all instance of mach/clk.h Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: use to_clk_periph_gate().] Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
The device tree binding models Tegra30 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: fixed typo in binding doc] Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The Tegra20 CAR (Clock And Reset) Controller controls most aspects of most clocks within Tegra20. The device tree binding models this as a single monolithic clock provider, which exports many clocks. This reduces the number of nodes needed in device tree to represent these clocks. This binding is only useful for Tegra20; the set of clocks that exists on Tegra30 is sufficiently different to merit its own binding. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Simon Glass <sjg@chromium.org> [pgaikwad: Added mux clk ids and sorted CAR node] Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra. Move the tegra_cpu_car_ops to include/linux/clk/tegra.h. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add function to read chip id from APB MISC registers. This function will also get called from clock driver to flush write operations on apb bus. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The "sleep.S" file has many functions that be shared by different module currently. Not just for CPU idle driver. Make it build as default now. Reported-by:
Rhyland Klein <rklein@nvidia.com> Signed-off-by:
Joseph Lo <josephl@nvidia.com> [swarren: add sleep.o to separate line so each line only contains 1 file] Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
It would rather to use the API of time_to_jiffies than a constant number of jiffies for the wait time of CPU power up. Based on the work by: Sang-Hun Lee <sanlee@nvidia.com> Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The reset handler code is used for either UP or SMP. To make Tegra device can compile for UP. It needs to be moved to another file that is not SMP only. This is because the reset handler also be needed by CPU idle "powered-down" mode. So we also need to put the reset handler init function in non-SMP only and init them always. And currently the implementation of the reset handler to know which CPU is OK to bring up was identital with "cpu_present_mask". But the "cpu_present_mask" did not initialize yet when the reset handler init function was moved to init early function. We use the "cpu_possible_mask" to replace "cpu_present_mask". Then it can work on both UP and SMP case. Signed-off-by:
Joseph Lo <josephl@nvidia.com> [swarren: dropped the move of v7_invalidate_l1() from one file to another, to avoid conflicts with Pavel's cleanup of this function, adjust Makefile so each line only contains 1 file.] Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Santosh Shilimkar authored
Drop the define and make use of scu_a9_get_base() which reads the physical address of SCU from CP15 register. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU. Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Acked-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add API to detect SCU base address from CP15. Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Acked-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
SCU based detection only works with Cortex-A9 MP and it doesn't support ones with multiple clusters. The only way to detect number of CPU core correctly is with DT /cpu node. Tegra SoCs decided to use DT detection as the only way and to not use SCU based detection at all. Even if DT /cpu node based detection fails, it continues with a single core Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add CPU node for Tegra30. Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
Add CPU node for Tegra20. Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
There are some redundant codes in the CPUINIT section that was caused by some codes not be organized well in "headsmp.S". Currently all the codes in "headsmp.S" were put into CPUINIT section. But actually it doesn't need to be loacted in CPUINIT section. There is no fuction access them in CPUINIT section and we will relocate them to IRAM. These codes also caused some unnecessary functions that access these codes been put into CPUINIT section too. This patch clean it up and put them into normal text section. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The tegra_cpu_die was be executed by the CPU itslf. So the clock gating procedure won't be executed after the CPU hardware shutdown code. Moving the clock gating procedure to tegra_cpu_kill that will be run by another CPU after the CPU died. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Acked-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
Updating the cache maintenance order before CPU shutdown when doing CPU hotplug. The old order: * clean L1 by flush_cache_all * exit SMP * CPU shutdown Adapt to: * disable L1 data cache by clear C bit * clean L1 by v7_flush_dcache_louis * exit SMP * CPU shutdown For CPU hotplug case, it's no need to do "flush_cache_all". And we should disable L1 data cache before clean L1 data cache. Then leaving the SMP coherency. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Acked-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The power up sequence is different on the cold boot CPU and the CPU that resumed from the hotplug. For the cold boot CPU, it was been power gated as default. To power up the cold boot CPU, the power should be un-gated by un toggling the power gate register manually. For the CPU that resumed from the hotplug, after un-halted the CPU. The flow controller will un-gate the power of the CPU. No need to manually control, just wait the power be resumed and continue the power up sequence after the CPU power is ready. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by:
Joseph Lo <josephl@nvidia.com> Acked-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Richard Zhao authored
tegra_cpu_init/exit will be called every time one cpu core is online or offline. And all cpu cores share same clocks, redundant clk_get/put wast time, so I move them out. Signed-off-by:
Richard Zhao <linuxzsc@gmail.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Fix: warning: (ARCH_TEGRA_2x_SOC) selects ARM_ERRATA_754327 which has unmet direct dependencies (CPU_V7 && SMP) warning: (ARCH_TEGRA_2x_SOC) selects ARM_ERRATA_742230 which has unmet direct dependencies (CPU_V7 && SMP) by selecting options only if SMP. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Hiroshi Doyu authored
No need to be public. Checked with: $ touch arch/arm/mach-tegra/*[ch] && make C=1 Signed-off-by:
Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Move arch/arm/mach-tegra/timer.c to drivers/clocksource/tegra20_timer.c so that the code is co-located with other clocksource drivers, and to reduce the size of the mach-tegra directory. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- Jan 19, 2013
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Mark Rutland authored
Currently __hw_perf_event_init has an err variable that's ignored right until the end, where it's initialised, conditionally set, and then used as a boolean flag deciding whether to return another error code. This patch removes the err variable and simplifies the associated error handling logic. Signed-off-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Will Deacon <will.deacon@arm.com>
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