- Aug 05, 2014
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Mario Kleiner authored
HDMI spec requires a valid max_tmds_clock from edid for hdmi deep color modes. If a sink violates this, disable deep color. Also add a hint to user about the deep_color module parameter if deep color is disabled due to that. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mario Kleiner authored
Skip the "manual" pageflip completion checks via polling and guessing in the vblank handler radeon_crtc_handle_vblank() on asics which are known to reliably support hw pageflip completion irqs. Those pflip irqs are a more reliable and race-free method of handling pageflip completion detection, whereas the "classic" polling method has some small races in combination with dpm on, and with the reworked pageflip implementation since Linux 3.16. On old asics without pflip irqs, the classic method is used. On asics with known good pflip irqs, only pflip irqs are used by default, but a new module parameter "use_pflipirqs" allows to override this in case we encounter asics in the wild with unreliable or faulty pflip irqs. A module parameter of 0 allows to use the classic method only in such a case. A parameter of 1 allows to use both classic method and pflip irqs as additional band-aid to avoid some small races which could happen with the classic method alone. The setting 1 gives Linux 3.16 behaviour. Hw pflip irqs are available since R600. Tested on DCE-4, AMD Cedar - FirePro 2270. v2: agd5f: only enable pflip interrupts on DCE4+ as they are not reliable on older asics. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andreas Boll authored
Adjust the previous tweak for hawaii to return 3 if the new firmware is used. Signed-off-by:
Andreas Boll <andreas.boll.dev@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Older firmware didn't support the new nop packet. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Andreas Boll <andreas.boll.dev@gmail.com>
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Alex Deucher authored
Return 2 so we can be sure the kernel has the necessary changes for acceleration to work. Note: This patch depends on these two commits: - drm/radeon: fix cut and paste issue for hawaii. - drm/radeon: use packet2 for nop on hawaii with old firmware Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Andreas Boll <andreas.boll.dev@gmail.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
Older firmware didn't support the new nop packet. v2 (Andreas Boll): - Drop usage of packet3 for new firmware Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by:
Andreas Boll <andreas.boll.dev@gmail.com> Cc: stable@vger.kernel.org
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Christian König authored
That should allow us to allocate bigger BOs. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Move the decision what to use into the common VM code. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
This closes a small window where the GPU might have accessed freed up memory. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
To be consistent with radeon_bo_unref, needed in the following patch. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
It's causing lockdep warnings and why should we access the memory that is freed up? Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
v2: rebase on vm_size scale change. Adjust vm_size default to 8, Better handle the default and smaller values. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Let's try to fix bugs related to this instead of just disabling it. Signed-off-by:
Christian König <christian.koenig@amd.com> Tested-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Scales much better than scanning the address range linearly. v2: store pfn instead of address Signed-off-by:
Christian König <christian.koenig@amd.com> Tested-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Won't work anyway, instead WARN_ON if the VA list isn't empty when we free the BO. Signed-off-by:
Christian König <christian.koenig@amd.com> Tested-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Don't wait for the BO to be used again, just update the PT on the next VM use. v2: remove stray semicolon. Signed-off-by:
Christian König <christian.koenig@amd.com> Tested-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This patch depends on: e0792981 (drm/radeon/dpm: fix typo in vddci setup for eg/btc) bugs: https://bugs.freedesktop.org/show_bug.cgi?id=73053 https://bugzilla.kernel.org/show_bug.cgi?id=68571 Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
This patch depends on: b0880e87 (drm/radeon/dpm: fix vddci setup typo on cayman) bug: https://bugs.freedesktop.org/show_bug.cgi?id=69723 Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Michel Dänzer authored
The HDP cache only applies to CPU access to VRAM. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Some hawaii cards use a different method to fetch the voltage info from the vbios. bug: https://bugs.freedesktop.org/show_bug.cgi?id=74250 Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
Some hawaii boards use a different method for fetching the voltage information from the vbios. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Michel Dänzer authored
This ensures the GPU sees all previous CPU writes to VRAM, which makes it safe: * For userspace to stream data from CPU to GPU via VRAM instead of GTT * For IBs to be stored in VRAM instead of GTT * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush is performed via MMIO Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Michel Dänzer authored
And clean up the function comment a little. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Both on their own are complex enough. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Need to unblank the display when resuming the MC. No functional change as this code path is not currently hit. We always disable the displays entirely rather than just blanking them. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Seems to make VM flushes more stable on SI and CIK. v2: only use the PFP on the GFX ring on CIK Signed-off-by:
Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Michel Dänzer authored
For symmetry with other *_set_wptr hooks. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Michel Dänzer authored
Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Michel Dänzer authored
PCI GART doesn't support unsnooped access. AGP GART already uses write-combined CPU mappings. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Looks like the lm63 driver supports the lm64 as well. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
It's only used in radeon_connectors.c. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
That didn't worked correctly any more and opened up a security problem. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Unused and unimplemented. Also fix specifying the kernel flag incorrectly at one occasion. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Some PX laptops seems to have problems turning the dGPU on/off. Add a quirk list to disable runpm by default on those systems. Also convert the current PX d3 delay handling to a quirk. bug: https://bugzilla.kernel.org/show_bug.cgi?id=51381 https://bugzilla.kernel.org/show_bug.cgi?id=74551 Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Now that fallback to gtt is fixed for cpu access, we can remove this limit. bug: https://bugs.freedesktop.org/show_bug.cgi?id=78717 v2: use new gart_pin_size to accurately track available gtt. v3: fix comment v4: clarify comment Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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Alex Deucher authored
Gives more accurate count and prevents failures when we can't allocate memory for the tests. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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Alex Deucher authored
Gives a more accurate limit than the previous code. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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Alex Deucher authored
So we know how large an allocation we can allow. v2: incorporate Michel's comments Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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