The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported
by the kernel test robot.

Fix the issue by removing the variable altogether and testing out the
return value of mtk_hdmi_pll_set_hw()

Fixes: 45810d48

 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230413-fixes-for-mt8195-hdmi-phy-v2-1-bbad62e64321@baylibre.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

DPHY RX module has a common module reset (RSTB_CMN) which is expected
to be released during configuration. In J721E SR1.0 the RSTB_CMN is
internally tied to CSI_RX_RST and is hardware controlled, for all
other newer platforms the common module reset is software controlled.
Add support to control common module reset during configuration and
also skip common module reset based on soc_device_match() for J721E SR1.0.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Jai Luthra <j-luthra@ti.com>
Link: https://lore.kernel.org/r/20230314073137.2153-1-vaishnav.a@ti.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Enable full rate divider configuration support for J721E_WIZ_16G for SGMII.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230309092434.443550-1-s-vadapalli@ti.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
additional PHY modes like QSGMII. Add a compatible for it.

Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230315092408.1722114-1-s-vadapalli@ti.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

In the wiz_mode_select() function, the configuration performed for
PHY_TYPE_USXGMII is unreachable. Fix it.

Fixes: b64a85fb

 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230403094552.929108-1-s-vadapalli@ti.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add register sequences for PCIe + SGMII PHY multilink configuration.
This has been validated on TI J7 platforms.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add support for the mediatek hdmi phy on MT8195 SoC

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Link: https://lore.kernel.org/r/20220919-v8-3-a84c80468fe9@baylibre.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Some phys, such as mt8195, needs to have a configure callback defined.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Link: https://lore.kernel.org/r/20220919-v8-2-a84c80468fe9@baylibre.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add a compatible for the HDMI PHY on MT8195

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Link: https://lore.kernel.org/r/20220919-v8-1-a84c80468fe9@baylibre.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The tegra_xusb_port_unregister should be called when usb2_port
and ulpi_port map fails in tegra_xusb_add_usb2_port() or in
tegra_xusb_add_ulpi_port(), fix it.

Fixes: 53d2a715

 ("phy: Add Tegra XUSB pad controller support")
Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20221129111634.1547747-1-cuigaosheng1@huawei.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Document the clock-output-names property of clock children, even though
the nodes are actually deprecated, to fix dtbs_check warnings like:

  k3-j7200-common-proc-board.dtb: wiz@5060000: refclk-dig: 'clock-output-names' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230404190115.546973-5-krzysztof.kozlowski@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The meta schema from DT schema already defines assigned-clocks, so there
is no need for device schema to mention it at all.  There are also no
benefits of having it here and a board could actually need more of clock
assignments than the schema allows.

Keep however the assigned-clocks in children nodes, as apparently their
proper parenting is required.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230404190115.546973-4-krzysztof.kozlowski@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The meta schema from DT schema already defines assigned-clocks, so there
is no need for device schema to mention it at all.  The specific
parenting of the first input and output clock is apparently important,
thus keep them as required, but without defining type.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230404190115.546973-3-krzysztof.kozlowski@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The meta schema from DT schema already defines assigned-clocks, so there
is no need for device schema to mention it at all.  There are also no
benefits of having it here and a board could actually need more of clock
assignments than the schema allows.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230404190115.546973-2-krzysztof.kozlowski@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The meta schema from DT schema already defines assigned-clocks, so there
is no need for device schema to mention it at all.  There are also no
benefits of having it here and a board could actually need more of clock
assignments than the schema allows.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230404190115.546973-1-krzysztof.kozlowski@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

clang with W=1 reports
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c:284:36: error:
  unused function 'hw_to_inno' [-Werror,-Wunused-function]
static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
                                   ^
This function is not used so remove it.

Signed-off-by: Tom Rix <trix@redhat.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Link: https://lore.kernel.org/r/20230324132649.2649166-1-trix@redhat.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add QMP PHY config for sa8775p and add support for the new compatible.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20230411130446.401440-4-brgl@bgdev.pl


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add a new compatible for the QMP UFS PHY found on sa8775p platforms and
update the clocks property to accommodate three clocks.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230411130446.401440-3-brgl@bgdev.pl


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The SDM845 QHP PHY doesn't have designated RX region. Corresponding RX
table is empty, so we can drop it completely.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230331151250.4049-2-dmitry.baryshkov@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

All PCIe PHYs on sc8180x platform have 2 lanes, so change the number of
lanes to 2.

Fixes: f839f14e

 ("phy: qcom-qmp: Add sc8180x PCIe support")
Cc: stable@vger.kernel.org # 5.15
Sgned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230331151250.4049-1-dmitry.baryshkov@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add the tables and constants for init sequences for UFS QMP phy found in
SM7150 SoC.

Signed-off-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230311231733.141806-3-danila@jiaxyga.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Document the QMP UFS PHY compatible for SM7150.

Signed-off-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230311231733.141806-2-danila@jiaxyga.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add support for RK3588 combo phy

This is based on prior work from XiaoDong Huang and
Peter Geis fixing this issue specifically for Rockchip 356x.

Co-developed-by: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
Link: https://lore.kernel.org/r/20230314135555.44162-4-lucas.tanure@collabora.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

RK3568 Naneng Combo Phy driver can support RK3588 with the additional
clocks and initial configuration, so add the compatible line.

Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230314135555.44162-3-lucas.tanure@collabora.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

PCIe for RK3588 is the same as RK3568.

Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230314135555.44162-2-lucas.tanure@collabora.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found
in SDX65.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1679035114-19879-2-git-send-email-quic_rohiagar@quicinc.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

clang with W=1 reports
drivers/phy/rockchip/phy-rockchip-pcie.c:122:19: error:
  unused function 'phy_rd_cfg' [-Werror,-Wunused-function]
static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
                  ^
This function is not used, so remove it.

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20230321122503.1783311-1-trix@redhat.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Replace the open-code with dev_err_probe() to simplify the code.

Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/202303231545522162256@zte.com.cn


Signed-off-by: Vinod Koul <vkoul@kernel.org>

According to commit 7945f929

 ("drivers: provide
devm_platform_ioremap_resource()"), convert platform_get_resource(),
devm_ioremap_resource() to a single call to use
devm_platform_ioremap_resource(), as this is exactly what this function
does.

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323073534.75037-1-yang.lee@linux.alibaba.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The qmp_combo_offsets_v3 table is already used for v3 and v4 PHYs. Reuse
it for v6 too, dropping the separate qmp_combo_offsets_v6.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323144726.1614344-2-dmitry.baryshkov@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

SM8350 and SM8450 use qmp_combo_offsets_v3 table, which doesn't have
PCS_USB offset. Add the usb3_pcs_usb entry to program correct registers
while setting up sm8350 and sm8450 USB+DP combo PHYs.

Fixes: 05bd1834

 ("phy: qcom-qmp-combo: Add config for SM6350")
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230323144726.1614344-1-dmitry.baryshkov@linaro.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for ti,tcan104x-can.yaml
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230320233955.2921179-1-robh@kernel.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Rather than requesting the parent reference clocks for the sierra PHY PLLs
and then assigning the parents as a struct clk. Use the clk_parent_data
feature for the clock framework and only specify the firmware names of the
parent clocks.

The clock framework internally will then translate this to the actual
clocks. This allows to remove a bit of boilerplate code.

It also allows to only specify a single reference clock for both PLLs,
which is a valid use case. The clock framework can handle the case where
not all inputs for a clock mux are connected, while the custom
implementation in the driver could not.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230326011416.363318-2-lars@metafoo.de


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The `devm_clk_register()` API is deprecated. Switch to
`devm_clk_hw_register()`.

Since the driver enables its own internal PLLs using the clock API we
still need to get a reference to the PLL clocks using the
`devm_clk_hw_get_clk()` API.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230326011416.363318-1-lars@metafoo.de


Signed-off-by: Vinod Koul <vkoul@kernel.org>

SGMII is validated on kria KR260 robotics starter kit. So modify the
comment description to include it in supported controllers list.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/1679940407-13131-1-git-send-email-radhey.shyam.pandey@amd.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

An minimum udelay of 200 us seems to be necessary on some machines. After
the setup of the pll, which needs about 100 us to be locked there seem
to be additional 100 us to get the phy really functional. Without this
delay the usb runs not functional. With this additional short udelay
this issue was not reported again.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20230227151318.1894938-1-m.grzeschik@pengutronix.de


Signed-off-by: Vinod Koul <vkoul@kernel.org>

The X-Gene PHY driver is unlikely to be useful on a kernel without general
X-Gene support enabled but currently only depends on arm64 rather than the
specific platform support. Narrow the dependency to ARCH_XGENE like we do
for other X-Gene specific drivers to ensure that users who have configured
down the set of platforms enabled don't see the option.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230221-phy-build-deps-v1-1-7091bcbd16b0@kernel.org


Signed-off-by: Vinod Koul <vkoul@kernel.org>

This commit introduces _poll_timeout functions usage instead of
wait loops waiting for a status bit.

Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20230210224309.98452-1-avolmat@me.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add new registers programming in sleepwalk sequence for Tegra234:
MASTER_ENABLE_A/B/C/D in XUSB_AO_UTMIP_SLEEPWALK.

Signed-off-by: Henry Lin <henryl@nvidia.com>
Signed-off-by: Haotien Hsu <haotienh@nvidia.com>
Link: https://lore.kernel.org/r/20230309061708.4156383-1-haotienh@nvidia.com


Signed-off-by: Vinod Koul <vkoul@kernel.org>