phy: cadence: Sierra: Use clk_parent_data to provide parent information

Rather than requesting the parent reference clocks for the sierra PHY PLLs
and then assigning the parents as a struct clk. Use the clk_parent_data
feature for the clock framework and only specify the firmware names of the
parent clocks.

The clock framework internally will then translate this to the actual
clocks. This allows to remove a bit of boilerplate code.

It also allows to only specify a single reference clock for both PLLs,
which is a valid use case. The clock framework can handle the case where
not all inputs for a clock mux are connected, while the custom
implementation in the driver could not.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230326011416.363318-2-lars@metafoo.de


Signed-off-by: Vinod Koul <vkoul@kernel.org>