- May 16, 2015
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Joachim Eastwood authored
Adds basic support for Embedded Artists' LPC4357 Developer's Kit. Board features a LPC4357 Soc, 32 MB SDRAM, 128 MB NAND Flash, 16 MB SPI Flash, USB and Ethernet. More information can be found on: http://www.embeddedartists.com/products/kits/lpc4357_kit.php Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Joachim Eastwood authored
NXP LPC18xx/43xx SoCs are very similar devices and should be able to share a common base (lpc18xx.dtsi). Diffences between the devices are put in a dtsi which is specific to that device. Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Maxime Coquelin authored
Tested-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- May 15, 2015
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Linus Walleij authored
The Ux500 like other Cortex-A9 SoC's has a Snoop Control Unit (SCU) and a Watchdog in the same address range as the local timers. Add these to the SoC device tree. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- May 14, 2015
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Lee Jones authored
This patch fixes a regression where serial is enabled by the first (board) DTSI, then disabled by the second (SoC) file. To enable serial and keep it enabled, we need to include the file which enables it last. Reported-by:
LAVA [via Peter Griffin <peter.griffin@linaro.org>]> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Eric Anholt authored
There exists a tiny MMU, configurable only by the VC (running the closed firmware), which maps from the ARM's physical addresses to bus addresses. These bus addresses determine the caching behavior in the VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top 2 bits. The bits in the bus address mean: From the VideoCore processor: 0x0... L1 and L2 cache allocating and coherent 0x4... L1 non-allocating, but coherent. L2 allocating and coherent 0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent From the GPU peripherals (note: all peripherals bypass the L1 cache. The ARM will see this view once through the VC MMU): 0x0... Do not use 0x4... L1 non-allocating, and incoherent. L2 allocating and coherent. 0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent The 2835 firmware always configures the MMU to turn ARM physical addresses with 0x0 top bits to 0x4, meaning present in L2 but incoherent with L1. However, any bus addresses we were generating in the kernel to be passed to a device had 0x0 bits. That would be a reserved (possibly totally incoherent) value if sent to a GPU peripheral like USB, or L1 allocating if sent to the VC (like a firmware property request). By setting dma-ranges, all of the devices below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and friends return addresses with 0x4 bits and avoid cache incoherency. This matches the behavior in the downstream 2708 kernel (see BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h). Signed-off-by:
Eric Anholt <eric@anholt.net> Tested-by:
Noralf Trønnes <noralf@tronnes.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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Eric Anholt authored
Signed-off-by:
Eric Anholt <eric@anholt.net> Acked-by:
Lee Jones <lee.jones@linaro.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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Baruch Siach authored
Device tree node names should contain the node's reg property address value. The i2c0 node was apparently forgotten in commit 25b2f1bd (ARM: bcm2835: node name unit address cleanup). Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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Stefan Wahren authored
This patch converts all bcm2835 dts and dtsi files to use the pinctrl header file. Reviewed-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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Rafał Miłecki authored
Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Rafał Miłecki authored
Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Florian Fainelli authored
Add a "brcm,bcm6328-timer" and "syscon-reboot" nodes to allow the generic syscon-reboot driver to reset a BCM63138 SoC. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Brian Norris authored
Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Ray Jui authored
Enable NAND support for Broadcom Cygnus SoC Signed-off-by:
Ray Jui <rjui@broadcom.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Brian Norris authored
Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Tested-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Brian Norris authored
Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Rafał Miłecki authored
Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Felix Fietkau authored
Signed-off-by:
Felix Fietkau <nbd@openwrt.org> Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Felix Fietkau authored
Signed-off-by:
Felix Fietkau <nbd@openwrt.org> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Florian Fainelli authored
Update bcm63138.dtsi with the following: - enable-method for both CPU nodes - brcm,bcm63138-bootlut node - resets properties to point to the correct PMB controller to release the secondary CPU from reset Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Florian Fainelli authored
Add the two BCM63138 PMB busses nodes found on this System-on-a-Chip as described in their corresponding binding document. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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- May 13, 2015
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Dinh Nguyen authored
Add the dts node for the A9 SCU. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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Linus Walleij authored
This adds the device tree data for the LIS331DL and the AK8974 magnetometer to the STUIB board device tree include file. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
The ST sensors on the Ux500 boards were not utilizing the IRQs for data ready sample triggers. Enable this by assigning the right GPIO lines and interrupt lines (when the GPIO lines are used for IRQs) to the accelerometer, gyro and magnetometer sensors. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
The magnetometer found on the Ux500 TVK and Snowball boards is a LSM303DLH not a LSM303DLM, small differences but still different. Put in the right compatible strings and things start working smoothly. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This registers all the CoreSight blocks on the DB8500 SoC: each core has a PTM (v1.0, r1p0-00rel0) connected, both connected to a funnel (DK-TM908-r0p1-00rel0) which in turn connects to a replicator (DM-TM909-r0p1-00rel0). The replicator has two outputs, port 0 to a TPIU interface and port 1 to an ETB (DK-TM907-r0p3-00rel0). The CoreSight blocks are all clocked by the APEATCLK from the PRCMU and their AHB interconnect is clocked from a separate clock called APETRACECLK. The SoC also has a CTI/CTM block which can be added later as we have upstream support in the CoreSight subsystem. Acked-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Lee Jones authored
This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Here we are enabling PMU IRQs on both channels. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
This is ARM's generic Performance Monitoring Unit. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Here we are enabling PMU IRQs on both channels. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
This is ARM's generic Performance Monitoring Unit. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
All the infrastructure is now in place for ST's PWM controller. This patch takes the final step and enables the IP on the 2020 Rev-E development platform. Signed-off-by:
Ajit Pal Singh <ajitpal.singh@st.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
Supply top level nodes for the STiH416 based development boards. The Pinctrl configuration has already been applied, so the only missing piece of the DT puzzle is for a board's DTB to enable the nodes. Signed-off-by:
Ajit Pal Singh <ajitpal.singh@st.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
Supply the Pinctrl configuration to enable PWM{0,1} lines on STiH416 based development boards. Signed-off-by:
Ajit Pal Singh <ajitpal.singh@st.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Lee Jones authored
Supply top level nodes for the STiH407 based development boards. The Pinctrl configuration has already been applied, so the only missing piece of the DT puzzle is for a board's DTB to enable the nodes. Signed-off-by:
Ajit Pal Singh <ajitpal.singh@st.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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Robert Jarzmik authored
Each pxa has an embedded OS Timers IP. The kernel cannot work without a valid clocksource, and this adds the OS Timers to the pxa device-tree description. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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Robert Jarzmik authored
Each pxa27x has an embedded keypad controller. Add it in the pxa27x device-tree description. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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Robert Jarzmik authored
Each pxa27x has an embedded usb udc controller. Add it in the pxa27x device-tree description. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr>
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