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  1. Mar 08, 2016
    • Ido Schimmel's avatar
      mlxsw: pci: Correctly determine if descriptor queue is full · 5091730d
      Ido Schimmel authored
      The descriptor queues for sending (SDQs) and receiving (RDQs) packets
      are managed by two counters - producer and consumer - which are both
      16-bit in size. A queue is considered full when the difference between
      the two equals the queue's maximum number of descriptors.
      
      However, if the producer counter overflows, then it's possible for the
      full queue check to fail, as it doesn't take the overflow into account.
      In such a case, descriptors already passed to the device - but for which
      a completion has yet to be posted - will be overwritten, thereby causing
      undefined behavior. The above can be achieved under heavy load (~30
      netperf instances).
      
      Fix that by casting the subtraction result to u16, preventing it from
      being treated as a signed integer.
      
      Fixes: eda6500a
      
       ("mlxsw: Add PCI bus implementation")
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5091730d
    • Ido Schimmel's avatar
      mlxsw: spectrum: Always decrement bridge's ref count · 912b1c89
      Ido Schimmel authored
      Since we only support one VLAN filtering bridge we need to associate a
      reference count with it, so that when the last port netdev leaves it, we
      would know that a different bridge can be offloaded to hardware.
      
      When a LAG device is memeber in a bridge and port netdevs are leaving
      the LAG, we should always decrement the bridge's reference count, as it's
      incremented for any port in the LAG.
      
      Fixes: 4dc236c3
      
       ("mlxsw: spectrum: Handle port leaving LAG while bridged")
      Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
      Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      912b1c89
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