- Jun 28, 2016
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Linus Walleij authored
This is the first Dragonboard based on APQ8060 and PM8058. It was produced in 2011 in cooperation between Qualcomm and BSQUARE. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Linus Walleij authored
There is currently a fixed regulator in the .dtsi file for the MSM8660 chipset, used by the SURF board. We want to define real regulators for a board using this chipset, so push the fixed regulator down to the SURF board which is the only user. Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Linus Walleij authored
The RTC was defined on 0x11d but on the MSM8660/APQ8060 it is actually on 0x1e8. We were saved by the fact that the driver does not use the reg parameter: instead it uses the compatible string to figure out where the RTC is. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Linus Walleij authored
The I2C block on the GSBI12 is used on the APQ8060 Dragonboard for sensors. Make it available in the chipset file. Take this opportunity to fix the IRQ flag "0" to "NONE" using the IRQ DT include. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Linus Walleij authored
This adds the L2CC IPC resource and RPM devices plus the nodes for the PM8901 and PM8058 regulators to the MSM8660 device tree. This was tested on the APQ8060 Dragonboard. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Linus Walleij authored
The SDCC5 SD/MMC controller is used for a second uSD slot on the APQ8060 Dragonboard. On most other systems it is just dark silicon so define it and leave it as "disabled" in the core SoC file. Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Linus Walleij authored
This adds the 8660 PMIC GPIO and MPP blocks to the MSM8660 DTSI. Verified against the vendor tree to be in these locations with these interrupts, tested on the APQ8060 Dragonboard. Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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John Stultz authored
Since the pmic8xxx-pwrkey driver is already supported in the qcom-apq8064.dtsi, and the pmic8xxx-pwrkey supports logic to configure proper device shutdown when ps_hold goes low, it is better to use that driver then a generic gpio button. Thus this patch remove the gpio power key entry here, so we don't get double input events from having two drivers enabled. Cc: Rob Herring <robh+dt@kernel.org> Cc: Andy Gross <agross@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Andy Gross authored
This patch updates the qcom,state-cells to qcom,smem-state-cells to match recent changes to the binding. Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Andy Gross authored
This patch adds the qcom,controlled-remotely property for the blsp2_bam controller node. This board requires this, otherwise the board fails to boot due to access of protected registers during BAM initialization. Fixes: 62bc8179 dts: msm8974: Add blsp2_bam dma node Signed-off-by:
Andy Gross <andy.gross@linaro.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Parth Pancholi authored
This board locks up if we stress test the eMMC, as the regulator s4 is unable to supply enough current for all the peripherials attached to it. As this supply is wired up to most of the peripherials including DDR, it resulted in such lockup. This patch fixes this issue by setting s4 regulator correctly with Auto power mode. Reported-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> [Srinivas Kandagatla: rewrote the change log] Tested-by:
Girish Sharma <girish.sharma@einfochips.com> Signed-off-by:
Parth Pancholi <parth.pancholi@einfochips.com> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Srinivas Kandagatla authored
This board has been renamed recently and announced at https://eragon.einfochips.com/products/sd-600eval.html So rename this board files so that it reflects actual product in market. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Srinivas Kandagatla authored
This patch move sdcc3 pinctrl nodes out of board file, so that other boards do not duplicate the same thing. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Srinivas Kandagatla authored
This patch moves out the sdcc1 pinctrl nodes out of board files to soc file, so that it will be duplicated in other board files. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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- Jun 12, 2016
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Andy Gross authored
This patch adds the firmware node for the APQ8064 Signed-off-by:
Andy Gross <andy.gross@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org>
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Andy Gross authored
This patch adds the Qualcomm SCM firmware node. Signed-off-by:
Andy Gross <andy.gross@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org>
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Andy Gross authored
This patch adds the firmware node for the SCM Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org>
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Andy Gross authored
This patch adds the power key device tree node. Signed-off-by:
Andy Gross <andy.gross@linaro.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Andy Gross authored
The #size-cells for the pmics are 0, but we specify a size in the reg property so that MPP and GPIO modules can figure out how many pins there are. Now that we've done that by counting irqs, we can remove the size elements in the reg properties and be DT compliant. Signed-off-by:
Andy Gross <andy.gross@linaro.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Stephen Boyd authored
Enable the sdcard slot and wire up the regulators for the two storage controllers found on the apq8074 dragonboard. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Stephen Boyd authored
Add the appropriate min/max voltages for the regulators on the apq8074 dragonboard so that they can be used by clients properly. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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- Jun 11, 2016
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Andy Gross authored
This adds back the dma channels for the i2c1 node. This is safe now that the qcom,controlled-remotely changes are in place and will be used on the boards that require it. This reverts commit 10c0f0e9.
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Andy Gross authored
This puts back in place the blsp2_bam node. This can be safely added due to the addition of the special qcom,controlled-remotely flag that will be used on specific boards that require it. This reverts commit 338d5188.
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- May 29, 2016
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George Spelvin authored
This will improve the performance of hash_32() and hash_64(), but due to complete lack of multi-bit shift instructions on H8, performance will still be bad in surrounding code. Designing H8-specific hash algorithms to work around that is a separate project. (But if the maintainers would like to get in touch...) Signed-off-by:
George Spelvin <linux@sciencehorizons.net> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: uclinux-h8-devel@lists.sourceforge.jp
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George Spelvin authored
Microblaze is an FPGA soft core that can be configured various ways. If it is configured without a multiplier, the standard __hash_32() will require a call to __mulsi3, which is a slow software loop. Instead, use a shift-and-add sequence for the constant multiply. GCC knows how to do this, but it's not as clever as some. Signed-off-by:
George Spelvin <linux@sciencehorizons.net> Cc: Alistair Francis <alistair.francis@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
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George Spelvin authored
This provides a multiply by constant GOLDEN_RATIO_32 = 0x61C88647 for the original mc68000, which lacks a 32x32-bit multiply instruction. Yes, the amount of optimization effort put in is excessive. :-) Shift-add chain found by Yevgen Voronenko's Hcub algorithm at http://spiral.ece.cmu.edu/mcm/gen.html Signed-off-by:
George Spelvin <linux@sciencehorizons.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Andreas Schwab <schwab@linux-m68k.org> Cc: Philippe De Muyter <phdm@macq.eu> Cc: linux-m68k@lists.linux-m68k.org
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George Spelvin authored
This is just the infrastructure; there are no users yet. This is modelled on CONFIG_ARCH_RANDOM; a CONFIG_ symbol declares the existence of <asm/hash.h>. That file may define its own versions of various functions, and define HAVE_* symbols (no CONFIG_ prefix!) to suppress the generic ones. Included is a self-test (in lib/test_hash.c) that verifies the basics. It is NOT in general required that the arch-specific functions compute the same thing as the generic, but if a HAVE_* symbol is defined with the value 1, then equality is tested. Signed-off-by:
George Spelvin <linux@sciencehorizons.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Andreas Schwab <schwab@linux-m68k.org> Cc: Philippe De Muyter <phdm@macq.eu> Cc: linux-m68k@lists.linux-m68k.org Cc: Alistair Francis <alistai@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: uclinux-h8-devel@lists.sourceforge.jp
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- May 28, 2016
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Anna-Maria Gleixner authored
The corresponding FROZEN hotplug notifier transitions used on suspend/resume are ignored. Therefore the switch case action argument is masked with the frozen hotplug notifier transition mask. Signed-off-by:
Anna-Maria Gleixner <anna-maria@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: rt@linutronix.de Patchwork: https://patchwork.linux-mips.org/patch/13351/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
MicroMIPS kernels may be expected to run on microMIPS only cores which don't support the normal MIPS instruction set, so be sure to pass the -mmicromips flag through to the VDSO cflags. Fixes: ebb5e78c ("MIPS: Initial implementation of a VDSO") Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.4.x- Patchwork: https://patchwork.linux-mips.org/patch/13349/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
In microMIPS kernels, handle_signal() sets the isa16 mode bit in the vdso address so that the sigreturn trampolines (which are offset from the VDSO) get executed as microMIPS. However commit ebb5e78c ("MIPS: Initial implementation of a VDSO") changed the offsets to come from the VDSO image, which already have the isa16 mode bit set correctly since they're extracted from the VDSO shared library symbol table. Drop the isa16 mode bit handling from handle_signal() to fix sigreturn for cores which support both microMIPS and normal MIPS. This doesn't fix microMIPS only cores, since the VDSO is still built for normal MIPS, but thats a separate problem. Fixes: ebb5e78c ("MIPS: Initial implementation of a VDSO") Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.4.x- Patchwork: https://patchwork.linux-mips.org/patch/13348/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Antony Pavlov authored
Here is the quote from [1]: The unit-address must match the first address specified in the reg property of the node. If the node has no reg property, the @ and unit-address must be omitted and the node-name alone differentiates the node from other nodes at the same level This patch adjusts MIPS dts-files and devicetree binding documentation in accordance with [1]. [1] Power.org(tm) Standard for Embedded Power Architecture(tm) Platform Requirements (ePAPR). Version 1.1 – 08 April 2011. Chapter 2.2.1.1 Node Name Requirements Signed-off-by:
Antony Pavlov <antonynpavlov@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13345/ Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Avoid an aliasing issue causing a build error in VDSO: In file included from include/linux/srcu.h:34:0, from include/linux/notifier.h:15, from ./arch/mips/include/asm/uprobes.h:9, from include/linux/uprobes.h:61, from include/linux/mm_types.h:13, from ./arch/mips/include/asm/vdso.h:14, from arch/mips/vdso/vdso.h:27, from arch/mips/vdso/gettimeofday.c:11: include/linux/workqueue.h: In function 'work_static': include/linux/workqueue.h:186:2: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing] return *work_data_bits(work) & WORK_STRUCT_STATIC; ^ cc1: all warnings being treated as errors make[2]: *** [arch/mips/vdso/gettimeofday.o] Error 1 with a CONFIG_DEBUG_OBJECTS_WORK configuration and GCC 5.2.0. Include `-fno-strict-aliasing' along with compiler options used, as required for kernel code, fixing a problem present since the introduction of VDSO with commit ebb5e78c ("MIPS: Initial implementation of a VDSO"). Thanks to Tejun for diagnosing this properly! Signed-off-by:
Maciej W. Rozycki <macro@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Fixes: ebb5e78c ("MIPS: Initial implementation of a VDSO") Cc: Tejun Heo <tj@kernel.org> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # v4.3+ Patchwork: https://patchwork.linux-mips.org/patch/13357/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Matt Redfearn authored
Allow KASLR to be selected on Pistachio based systems. Tested on a Creator Ci40. Signed-off-by:
Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jonas Gorski <jogo@openwrt.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13356/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Harvey Hunt authored
On certain MIPS32 devices, the ftrace tracer "function_graph" uses __lshrdi3() during the capturing of trace data. ftrace then attempts to trace __lshrdi3() which leads to infinite recursion and a stack overflow. Fix this by marking __lshrdi3() as notrace. Mark the other compiler intrinsics as notrace in case the compiler decides to use them in the ftrace path. Signed-off-by:
Harvey Hunt <harvey.hunt@imgtec.com> Cc: <linux-mips@linux-mips.org> Cc: <linux-kernel@vger.kernel.org> Cc: <stable@vger.kernel.org> # 4.2.x- Patchwork: https://patchwork.linux-mips.org/patch/13354/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
The Hardware page Table Walker (HTW) is being misconfigured on 64-bit kernels. The PWSize.PS (pointer size) bit determines whether pointers within directories are loaded as 32-bit or 64-bit addresses, but was never being set to 1 for 64-bit kernels where the unsigned long in pgd_t is 64-bits wide. This actually reduces rather than improves performance when the HTW is enabled on P6600 since the HTW is initiated lots, but walks are all aborted due I think to bad intermediate pointers. Since we were already taking the width of the PTEs into account by setting PWSize.PTEW, which is the left shift applied to the page table index *in addition to* the native pointer size, we also need to reduce PTEW by 1 when PS=1. This is done by calculating PTEW based on the relative size of pte_t compared to pgd_t. Finally in order for the HTW to be used when PS=1, the appropriate XK/XS/XU bits corresponding to the different 64-bit segments need to be set in PWCtl. We enable only XU for now to enable walking for XUSeg. Supporting walking for XKSeg would be a bit more involved so is left for a future patch. It would either require the use of a per-CPU top level base directory if supported by the HTW (a bit like pgd_current but with a second entry pointing at swapper_pg_dir), or the HTW would prepend bit 63 of the address to the global directory index which doesn't really match how we split user and kernel page directories. Fixes: cab25bc7 ("MIPS: Extend hardware table walking support to MIPS64") Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13364/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
Add field definitions for some of the 64-bit specific Hardware page Table Walker (HTW) register fields in PWSize and PWCtl, in preparation for fixing the 64-bit HTW configuration. Also print these fields out along with the others in print_htw_config(). Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13363/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
Simplify the DSP instruction wrapper macros which use explicit encodings for microMIPS and normal MIPS by using the new encoding macros and removing duplication. To me this makes it easier to read since it is much shorter, but it also ensures .insn is used, preventing objdump disassembling the microMIPS code as normal MIPS. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13314/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
Hardcoded MIPS instruction encodings are provided for tlbinvf, mfhc0 & mthc0 instructions, but microMIPS encodings are missing. I doubt any microMIPS cores exist at present which support these instructions, but the microMIPS encodings exist, and microMIPS cores may support them in the future. Add the missing microMIPS encodings using the new macros. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13313/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
When the toolchain doesn't support MSA we encode MSA instructions explicitly in assembly. Unfortunately we use .word for both MIPS and microMIPS encodings which is wrong, since 32-bit microMIPS instructions are made up from a pair of halfwords. - The most significant halfword always comes first, so for little endian builds the halves will be emitted in the wrong order. - 32-bit alignment isn't guaranteed, so the assembler may insert a 16-bit nop instruction to pad the instruction stream to a 32-bit boundary. Use the new instruction encoding macros to encode microMIPS MSA instructions correctly. Fixes: d96cc3d1 ("MIPS: Add microMIPS MSA support.") Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13312/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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James Hogan authored
Toolchains may be used which support microMIPS but not VZ instructions (i.e. binutis 2.22 & 2.23), so extend the explicitly encoded versions of the guest COP0 register & guest TLB access macros to support microMIPS encodings too, using the new macros. This prevents non-microMIPS instructions being executed in microMIPS mode during CPU probe on cores supporting VZ (e.g. M5150), which cause reserved instruction exceptions early during boot. Fixes: bad50d79 ("MIPS: Fix VZ probe gas errors with binutils <2.24") Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13311/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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