- Jul 23, 2017
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Shawn Lin authored
Kill these two pinctrl reference totally from rk3399 as it never work indeed. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
pcie_clkreqn actually doesn't work at all, so replace it with pcie_clkreqn_cpm. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Caesar Wang authored
This patch enables the gpu and adds the mali-supply power for RK3399-GRU devices. Signed-off-by:
Caesar Wang <wxt@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Caesar Wang authored
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq opp table. RK3399 and RK3399-OP1 SoCs have a different recommendation table with gpu opp. Also, the ARM's mali driver found on https://developer.arm.com/products/software/mali-drivers/midgard-kernel . Signed-off-by:
Caesar Wang <wxt@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
keep-power-in-suspend was invented for SDIO only, so it should not be used for eMMC node. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Jul 16, 2017
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Shawn Lin authored
We deprecated the "num-slots" property now and plan to get rid of it finally. Just move a step to cleanup it from DT. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
pcie_clkreqn actually doesn't work at all, so replace it with pcie_clkreqn_cpm. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Caesar Wang authored
The SdioAudio power domain includes the i2s/spdif/spi5/sdio. So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order to save more power consumption. Signed-off-by:
Caesar Wang <wxt@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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William Wu authored
Rockchip's RK3328 evaluation board has one usb2 otg controller and one usb2 host controller which consist of EHCI and OHCI. Each usb controller connects with one usb2 phy port through UTMI+ interface. Let's enable them to support usb2 on RK3328 evaluation board. Signed-off-by:
William Wu <william.wu@rock-chips.com> [restructured enablement of u2phy subnodes] Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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William Wu authored
This patch adds usb2 otg/host controllers and phys nodes for Rockchip RK3328 SoCs. Signed-off-by:
William Wu <william.wu@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
Provide the dynamic power coefficient of the big and little CPU clusters. These numbers are currently in use on the Samsung Chromebook Plus ("Kevin"). The power allocator thermal governor doesn't know how to do anything if it doesn't get power parameters from its cooling devices (in this case, CPUfreq). So this effectively enables the power-allocator governor. Signed-off-by:
Brian Norris <briannorris@chromium.org> [set the property in each core node] Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Matthias Kaehlcke authored
The Gru device tree currently contains entries for the regulators ppvar_bigcpu, ppvar_litcpu, ppvar_gpu and ppvar_centerlogic; however, the regulators have not been enabled, due to the lack of binding and driver support for keeping the over-voltage protection (OVP) at bay and preventing unintended regulator shutdowns on voltage downshifts. Now, the vctrl regulator driver has been merged, along with new bindings for asymmetric settling time. The driver is OVP aware, it splits larger voltage decreases in multiple steps when necessary and adds required delays. This change renames each of the aforementioned regulators to <orig_name>_pwm and adds a new vctrl regulator named <orig_name>. The vctrl regulators use the voltage of their corresponding PWM regulator as control voltage. The OVP related values are empirical and stem from the Chrome OS kernel tree. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Brian Norris <briannorris@chromium.org> [fixed node names and parent supplies of gpu and centerlogic] Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Matthias Kaehlcke authored
Gru derivatives besides Kevin have slightly different voltage ranges for their CPU regulators. Let's keep the base Gru file accurate and let Kevin override. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Brian Norris <briannorris@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Klaus Goger authored
replace all occurrences of sdmcc with sdmmc in the arm64 rockchip devicetree files. Signed-off-by:
Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Jul 03, 2017
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Marc Zyngier authored
Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult. Fixes: adbc3695 ("arm64: dts: add the Marvell Armada 3700 family and a development board") Cc: <stable@vger.kernel.org> Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Jul 02, 2017
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Maxime Ripard authored
This reverts commits 2c0cba48 ("arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module") to 2428fd0f ("arm64: defconfig: Enable dwmac-sun8i driver on defconfig") and 3432a86e ("arm: sun8i: orangepipc: use internal phy-mode") to 5a79b4f2 ("arm: sun8i: orangepi-2: use internal phy-mode") that should be merged through the arm-soc tree, and end up in merge conflicts and build failures. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- Jun 23, 2017
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Arnd Bergmann authored
As I found by chance while merging another patch, the usage of a dma-mask in this DT node is wrong for multiple reasons: - dma-masks are a Linux specific concept, not a general hardware feature - In DT, we use the "dma-ranges" property to describe how DMA addresses related between devices. - The 40-bit mask appears to be completely unnecessary here, as the SoC cannot address that much memory anyway, so simply asking for a 64-bit mask (as supported by the device) should succeed anyway. The patch to remove the parsing of the property is getting merged through the crypto tree. Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
This resolves a build error in the next/dt branch: In file included from arch/arm64/boot/dts/mediatek/mt6797-evb.dts:16:0: arch/arm64/boot/dts/mediatek/mt6797.dtsi:15:10: fatal error: dt-bindings/power/mt6797-power.h: No such file or directory 003f5d0c ("arm64: dts: mediatek: add clk and scp nodes for MT6797") Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Jerome Brunet authored
Add support for the CC board from Shenzhen Libre Technology More information about the board are available here: https://libre.computer/blog/ Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com>
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- Jun 21, 2017
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Thomas Petazzoni authored
This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files to describe the ICU and GICP units, and use ICU interrupts for all devices in the CP110 blocks. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Viresh Kumar authored
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by:
Krzysztof Kozlowski <krzk@kernel.org> Reported-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- Jun 20, 2017
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Gregory CLEMENT authored
Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs. The Armada 8K has two CP110 blocks, each having two GPIO controllers. However, in each CP110 block, one of the GPIO controller cannot be used: in the master CP110, only the second GPIO controller can be used, while on the slave CP110, only the first GPIO controller can be used. On the other side, the Armada 7K has only one CP110, but both its GPIO controllers can be used. For this reason, the GPIO controllers are marked as "disabled" in the armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only enabled in the per-SoC dtsi files. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs. The CP master being different between Armada 7k and Armada 8k. This commit introduces the intermediates files armada-70x0.dtsi and armada-80x0.dtsi. These new files will provide different compatible strings depending of the SoC family. They will also be the location for the pinmux configuration at the SoC level. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
The new binding for the system controller on cp110 moved the clock controller into a subnode. This preliminary step will allow to add gpio and pinctrl subnodes. Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
The *-clock-output-names of the cp110-system-controller0 node are not used anymore, so remove them. Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
New bindings are used for the system controller on the ap806, which means all clock properties must be converted. Use the new bindings in the xor nodes. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
Since the mdio nodes are disabled by default now, we should explicitly enable these nodes at the board level when they are used. Enable the cpm_mdio node for the 8040-mcbin. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Jun 19, 2017
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Andreas Färber authored
Add Device Trees for Actions Semiconductor S900 SoC and uCRobotics Bubblegum-96 board. UART0/1/4/6 interrupts are guesses. Cc: 96boards@ucrobotics.com Signed-off-by:
Andreas Färber <afaerber@suse.de>
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- Jun 17, 2017
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Antoine Tenart authored
Add the description of the xMDIO bus for the Marvell Armada 7k and Marvell Armada 8k; for both CP110 slave and master. This bus is found on Marvell Ethernet controllers and provides an interface with the xMDIO bus. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
The cryptographic engine found on the cp110 slave is disabled by default because of some known limitations. Add a comment to explain why it is disabled by default. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
The cryptographic engine on the master cp110 is now enabled by default at the SoC level. Remove its dts nodes that were only enabling it. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
Enable the cryptographic engine at the SoC level on the master cp110. This engine is always present and do not depends on any pinmux configuration. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
By adding this regulator, the SD cards are usable at higher speed protocols such as SDR104. This patch was tested with an SD HC card compatible with UHS-I. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Konstantin Porotchkin authored
The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second one. Moreover, the Armada 37xx DB v2 board populates the 2 SDHCI interfaces. The second interface is using pluggable module that can either have an SD connector or eMMC on it. This patch adds support for SD module in the device DT. [ gregory.clement@free-electrons.com: - Add more detail in commit log - Sort the dt node in address order - Document the SD slot in the dts ] Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
When several groups of register address and size are used with reg, then surround each one by angle bracket. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
This cosmetic patch aligns the compatible string when there are on several lines. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
The initial device tree file was for the board V1.4. Now the V2.0 board is also available. The same dtb will work for both, but the CON number have changed, so update the comment in the dts to reflect this. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
Sort the reference nodes in alphabetical order to ease the merge of future nodes. Reviewed-by:
Andreas Färber <afaerber@suse.de> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
Disable the mdio nodes by default in the cp110 slave and master dtsi as they're not wired on every board. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
Explicitly enable the MDIO nodes in the Marvell Armada 7k DB and Marvell Armada 8k DB. This is needed as the MDIO nodes will be disabled in the CP 110 slave and master dtsi by a following up patch. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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