- May 21, 2017
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Vanessa Maegima authored
Add the initial support for imx7d-pico board. Add support for eMMC, USB host, USB device, PMIC, Ethernet and audio. For more information about this board, please visit: http://www.technexion.org/products/pico/pico-som/pico-imx7-emmc Signed-off-by:
Vanessa Maegima <vanessa.maegima@nxp.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Stefan Agner authored
The PWM driver has now capability to specify the PWM polarity which is e.g. for backlight control. Allow to make use of PWM polarity by specifying pwm-cells to be 3 in the base dt. Signed-off-by:
Stefan Agner <stefan@agner.ch> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Andrey Smirnov authored
Enable PCIe peripheral on this board. Cc: yurovsky@gmail.com Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Andrey Smirnov authored
Cc: yurovsky@gmail.com Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Andrey Smirnov authored
Add node for U38, a 74LV595PW serial-in shift register that acts as a GPIO expander on the board. Cc: yurovsky@gmail.com Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Andrey Smirnov authored
List GPR block as compatible "fsl,imx6q-iomuxc-gpr" to support drivers requesting it that way (PCIe driver is one example). Cc: yurovsky@gmail.com Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Andrey Smirnov authored
Add node for GPC and specify as a parent interrupt controller for SoC bus. Cc: yurovsky@gmail.com Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Andrey Smirnov authored
Now that support for 'anatop-enable-bit' has been added to ANADIG driver, reintroduce 'anatop-enable-bit' for all applicable LDOs. Cc: yurovsky@gmail.com Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- May 18, 2017
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Fabio Estevam authored
On imx6sx-sdb rev B/C the VDD_ARM_IN and VDD_SOC_IN supplies are connected together and both are supplied by the SW1A PMIC output, so model this correctly in the device tree. Suggested-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- May 15, 2017
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Fabio Estevam authored
When running a stress playback/stop loop test on a mx6colibri channel swaps can be noticed randomly. Increasing the SGTL5000 LRCLK pad strength to its maximum value fixes the issue, so add the 'lrclk-strength' property to avoid the audio channel swaps. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Fabio Estevam authored
When running a stress playback/stop loop test on a mx6wandboard channel swaps can be noticed randomly. Increasing the SGTL5000 LRCLK pad strength to its maximum value fixes the issue, so add the 'lrclk-strength' property to avoid the audio channel swaps. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Stefan Agner authored
The USDHC instances need the USDHC NAND and IPG clock in order to operate. Reference them properly by replacing the dummy clocks with the actual clocks. Note that both clocks are currently implicitly enabled since they are part of the i.MX 7 clock drivers init_on list. This might change in the future. Signed-off-by:
Stefan Agner <stefan@agner.ch> Acked-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Alexandre Belloni authored
The rv4162 compatbile string is missing the vendor part, add it. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Alexandre Belloni authored
The rv4162 vendor is microcrystal, not ST. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Alexandre Belloni authored
The rv4162 vendor is microcrystal, not ST. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Tim Harvey authored
The Gateworks Ventana GW5600 is a media-centric single-board computer based on the NXP IMX6 SoC with the following features: * PoE (emulated 802.3af) * IMX6 DualLite Soc (supports IMX6S,IMX6DL,IMX6Q) * 1GiB DDR3 DRAM (supports up to 4GiB) * 8GB eMMC * 1x microSD connector * Gateworks System Controller: - hardware watchdog - hardware monitor - pushbutton controller - EEPROM storage - power control * 1x bi-color USER LED * 1x front-panel pushbutton * 1x front-panel GbE * 2x front panel USB 2.0 * 1x front panel USB OTG * 1x SIM socket * 1x miniPCIe socket with SATA (mSATA) * 1x miniPCIe socket with USB 2.0 (Modem) * 1x miniPCIe socket with PCIe, USB 2.0, and SIM * RS232/RS485 serial - 2x RS232 UARTs (off-board connector) - 1x RS485 (loading option) * 4x digital I/O signals (PWM/I2C/GPIO/5V/3.3V options) * 1x analog input (0 to 5V) * 1x CAN (loading option) * off-board LVDS: - I2C - 12V - LED driver (4x 330mA strings) - matrix keypad controller (8row x 10col) - I2S - dual-channel LVDS - PWM * off-board video input: - 16bit parallel / MIPI (IPU1_CSI0) * GPS (loading option) * Analog Video Input (CVBS) 3 inputs (1 active at a time) * Analog Audio Input/Output (2ch Line level, optional MIC/HP drivers) * HDMI out * JTAG programmable * Inertial Module Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Lucas Stach authored
Add the more specific QuadPlus compatible to the GPC node, to trigger the required workarounds in the power domain code. In regard to the interrupt mapping the QuadPlus controller is fully compatible to the Quad one, so keep that compatible in place. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Lucas Stach authored
Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Tim Harvey authored
Remove the sky2 ethernet device node from the pcie controller which was invalid to begin with. The original intent was to allow the bootloader to populate the MAC via dt but this requires the PCI bus topology to be complete in dt as well and as these boards have an expansion connector that topology is dynamic and can't be represented here. Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- Apr 21, 2017
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Viresh Kumar authored
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by:
Krzysztof Kozlowski <krzk@kernel.org> Reported-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by:
Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Acked-by:
Rob Herring <robh@kernel.org> [k.kozlowski: Split patch per ARM and ARM64] Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org>
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- Apr 19, 2017
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Thomas Petazzoni authored
The SPEAr600 has a built-in ADC, which already has a Device Tree binding described in Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt. This commit adds the description in the SPEAr600 Device Tree of this ADC device. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Thomas Petazzoni authored
The spear6xx doesn't have a pinctrl driver, since the pinmux is globally defined through a single register, generally configured by the firmware/bootloader. Therefore, the pinctrl related properties in spear600-evb.dts are not necessary. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Thomas Petazzoni authored
This commit moves spear600-evb.dts to use the new flash partition Device Tree binding documented in Documentation/devicetree/bindings/mtd/partition.txt. As this Device Tree binding document says: "For backwards compatibility partitions as direct subnodes of the mtd device are supported. This use is discouraged." Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Thomas Petazzoni authored
This commit fixes a minor coding style issue in spear600-evb.dts: missing spaces around equal sign. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Thomas Petazzoni authored
Now that we have introduced node labels in spear600.dtsi, we can use them for spear600-evb.dts. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Thomas Petazzoni authored
Having labels allows to more easily reference nodes in .dts files including spear600.dtsi. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Sudeep Holla authored
This patch fixes the following set of warnings on vexpress platforms: sysreg@010000 simple-bus unit address format error, expected "10000" sysctl@020000 simple-bus unit address format error, expected "20000" i2c@030000 simple-bus unit address format error, expected "30000" aaci@040000 simple-bus unit address format error, expected "40000" mmci@050000 simple-bus unit address format error, expected "50000" kmi@060000 simple-bus unit address format error, expected "60000" kmi@070000 simple-bus unit address format error, expected "70000" uart@090000 simple-bus unit address format error, expected "90000" uart@0a0000 simple-bus unit address format error, expected "a0000" uart@0b0000 simple-bus unit address format error, expected "b0000" uart@0c0000 simple-bus unit address format error, expected "c0000" wdt@0f0000 simple-bus unit address format error, expected "f0000" Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by:
Liviu Dudau <liviu.dudau@arm.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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- Apr 14, 2017
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Ludovic Desroches authored
Remove ADC channels that are not available by default on the sama5d3_xplained board (resistor not populated) in order to not create confusion. Signed-off-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Cc: <stable@vger.kernel.org> # 3.16+ Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Ludovic Desroches authored
The voltage reference for the ADC is not 3V but 3.3V since it is connected to VDDANA. Signed-off-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Cc: <stable@vger.kernel.org> # 3.16+ Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Peter Rosin authored
The envelope detector can analyze 6 different signals, selectable with a mux controlled by three gpio pins. Signed-off-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com>
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- Apr 12, 2017
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Benjamin Herrenschmidt authored
We found out that HW checksum generation only works from AST2500 onward. This disables it on AST2400 and removes the "no-hw-checksum" properties in the device-trees. The problem we had wasn't related to NC-SI. Also rework the logic testing for that property so it can be used to disable HW checksum generation and checking regardless of whether NC-SI is used or not in case other variants out there need this. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Benjamin Herrenschmidt authored
We test for aspeed chips to handle a couple of special cases, but we do that by checking the machine type which isn't right. Instead check the actual device compatible property. This also updates the dtsi files for the aspeed SoC to match. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Ralph Sennhauser authored
Recently most nodes got labels to make them referenceable. The USB 3.0 nodes as well as the nodes for the SATA controllers were left out, rectify the omission. The labels "sataX" are already used by some boards for the SATA ports, therefore use "ahciX" to label the SATA controller nodes. To avoid potential confusion by labeling an USB3.0 controller "usb2" use usb3_X as labels. This also coincides with the node names themselves (usb@xxxxx vs usb3@xxxxx). Signed-off-by:
Ralph Sennhauser <ralph.sennhauser@gmail.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Apr 11, 2017
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Hans Verkuil authored
Add the new hdmi phandle to exynos4.dtsi. This phandle is needed by the s5p-cec driver to initialize the CEC notifier framework. Tested with my Odroid U3. Signed-off-by:
Hans Verkuil <hans.verkuil@cisco.com> Tested-by:
Marek Szyprowski <m.szyprowski@samsung.com> CC: linux-samsung-soc@vger.kernel.org CC: devicetree@vger.kernel.org CC: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
Mauro Carvalho Chehab <mchehab@s-opensource.com>
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Benjamin Gaignard authored
To use CEC notifier sti CEC driver needs to get phandle of the hdmi device. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by:
Hans Verkuil <hans.verkuil@cisco.com> CC: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by:
Mauro Carvalho Chehab <mchehab@s-opensource.com>
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- Apr 10, 2017
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Christopher Spinrath authored
The hpd pin of the second hdmi connector of the Utilite Pro is wired up to a gpio pin of the SoC. Reflect this in the device tree. Signed-off-by:
Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Leonard Crestez authored
On imx6qp-sabresd LDO_ARM is connected to a different PMIC output than the other imx6qdl-sabresd boards. Setting cpu0 arm-supply to sw2_reg is wrong, this must have mistakenly slipped out of the vendor tree where this is are used for LDO bypass. Signed-off-by:
Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Leonard Crestez authored
Setting the supply is optional but beneficial, it will cause PMIC voltages to be dynamically changed with cpu frequency. Signed-off-by:
Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Tim Harvey authored
The Gateworks Ventana GW5903 is a single-board computer based on the NXP IMX6 SoC with the following features: * IMX6 DualLite Soc (supports IMX6S,IMX6DL,IMX6Q) * 4GiB DDR3 DRAM * 32GB eMMC * 1x microSD connector * Gateworks System Controller: - hardware watchdog - hardware monitor - pushbutton controller - EEPROM storage - power control * JTAG programmable * Inertial Module * uBlox EMMY-W1 (bluetooth/nfc/802.11ac) Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Martin Kaiser authored
The i.MX25 contains two AHB to IP bridges (AIPS), each of which has a set of control registers. Add the memory regions for the control registers to the Device Tree. Signed-off-by:
Martin Kaiser <martin@kaiser.cx> Reviewed-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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