- Jul 22, 2014
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Matthias Brugger authored
The Aquaris5 is a mobile phone based on the MT6589 SoC. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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Matthias Brugger authored
This adds a generic devicetree board file and a dtsi for boards based on MT6589 SoCs from Mediatek. Apart from the generic parts (gic, clocks) the only component currently supported are the timers. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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- Jul 19, 2014
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Mateusz Krawczuk authored
Add DTS for s5pc110 boards: goni, aquila, smdkc110 s5pv210: smdkv210, tiny210, torbreck Signed-off-by:
Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> [t.figa: Rebased, fixed merge conflicts, neatened.] Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Mateusz Krawczuk authored
Add generic device tree for s5pv210 and s5pv210-pinctrl Signed-off-by:
Mateusz Krawczuk <m.krawczuk@partner.samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jul 18, 2014
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Boris BREZILLON authored
The pwm driver requires a clocks property referencing the pwm peripheral clk. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
udphs_clk (USB Device Controller clock) is referenced instead of uhphs_clk (USB Host Controller clock). Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Bo Shen authored
Correct the typo error for the second "uhphs_clk". Signed-off-by:
Bo Shen <voice.shen@atmel.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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- Jul 15, 2014
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Suman Anna authored
DRA7xx has 13 system mailboxes, and is present on both the DRA72x and DRA74x family of SoCs. Add the DT nodes for all these 13 mailboxes. Except for mailbox 1, all other mailboxes do not have interrupts mapped into the MPU GIC by default. All the mailboxes have been disabled and the interrupts property information is left out intentionally for now, because of the dependencies against the crossbar driver. These mailboxes can be enabled when a usecase arises and the crossbar driver dependencies are met. NOTE: The mailbox 1 has different number of mailbox fifos and IP interrupts compared to the remaining 12 mailboxes. Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Suman Anna authored
The mailbox DT node for AM4372 is enabled and is corrected to remove some properties that have crept in by mistake. Fixes: 9e3269b8 (ARM: dts: AM4372: Add L2, EDMA, mailbox, MMC and SHAM nodes) Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Suman Anna authored
The mailbox DT node data has been added for AM33xx device. The mailbox IP in AM33xx is similar to the version found in OMAP4+ devices. Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Suman Anna authored
The mailbox DT node data has been added for OMAP44xx devices. Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Suman Anna authored
The number of mailbox fifos and users (IP interrupts) are added to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, and OMAP5 family of SoCs through the DT properties "ti,mbox-num-fifos" and "ti,mbox-num-users" properties. This data represents the same data that used to be represented in hwmod attribute data through the .num_fifos and .num_users fields previously. Signed-off-by:
Suman Anna <s-anna@ti.com> Acked-by:
Pavel Machek <pavel@ucw.cz> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Jul 14, 2014
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Andrew Lunn authored
Now that all boards have been converted to DT and all the support code lives in mach-mvebu, we can remove mach-kirkwood. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1405028192-9623-2-git-send-email-andrew@lunn.ch Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- Jul 13, 2014
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Bo Shen authored
Add clocks for usb device, or else switch to CCF, the gadget won't work. Reported-by:
Jiri Prchal <jiri.prchal@aksignal.cz> Signed-off-by:
Bo Shen <voice.shen@atmel.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by:
Jiri Prchal <jiri.prchal@aksignal.cz> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Jul 11, 2014
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Arun Kumar K authored
Adding the optional clock property for the mfc_pd for handling the re-parenting while pd on/off. Signed-off-by:
Arun Kumar K <arun.kk@samsung.com> Signed-off-by:
Shaik Ameer Basha <shaik.ameer@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jul 09, 2014
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Simon Horman authored
Unify white space usage by consistently using tabs for indentation. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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- Jul 08, 2014
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Andrii.Tseglytskyi authored
Add ABB device nodes for OMAP5 family of devices. Data is based on final production OMAP543x Technical Reference Manual revision Z (April 2013). Final production Data Manual for OMAP5432 SWPS050F(APRIL 2014). [nm@ti.com: co-developer and updates to latest documentation] Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Andrii.Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tushar Behera authored
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux. As per the user manual, it should be CLK_MAU_EPLL. The problem surfaced when the bootloader in Peach-pit board set the EPLL clock as the parent of AUDSS mux. While booting the kernel, we used to get a system hang during late boot if CLK_MAU_EPLL was disabled. Signed-off-by:
Tushar Behera <tushar.b@samsung.com> Signed-off-by:
Shaik Ameer Basha <shaik.ameer@samsung.com> Reported-by:
Kevin Hilman <khilman@linaro.org> Tested-by:
Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jul 07, 2014
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Enric Balletbo i Serra authored
As this board use external clock for RMII interface we should specify 'rmii' phy mode and 'rmii-clock-ext' to make ethernet working. Signed-off-by:
Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Peter Ujfalusi authored
The use of FIFO in McASP can reduce the risk of audio under/overrun and lowers the load on the memories since the DMA will operate in bursts. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Peter Ujfalusi authored
The use of FIFO in McASP can reduce the risk of audio under/overrun and lowers the load on the memories since the DMA will operate in bursts. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Roger Quadros authored
After clarification from the hardware team it was found that this 1.8V PHY supply can't be switched OFF when SoC is Active. Since the PHY IPs don't contain isolation logic built in the design to allow the power rail to be switched off, there is a very high risk of IP reliability and additional leakage paths which can result in additional power consumption. The only scenario where this rail can be switched off is part of Power on reset sequencing, but it needs to be kept always-on during operation. This patch is required for proper functionality of USB, SATA and PCIe on DRA7-evm. CC: Rajendra Nayak <rnayak@ti.com> CC: Tero Kristo <t-kristo@ti.com> Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Jul 05, 2014
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Jaewon Kim authored
pwm-cells should be 3. Third cell is optional PWM flags. And This flag supported by this binding is PWM_POLARITY_INVERTED. Signed-off-by:
Jaewon Kim <jaewon02.kim@samsung.com> Reviewed-by:
Sachin Kamat <sachin.kamat@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- Jul 04, 2014
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Rajendra Nayak authored
Without the patch: /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate 532000000 /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate 532000000 /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate 532000000 With the patch: /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate 532000000 /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate 266000000 /debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate 133000000 The l3 clock derived from core DPLL is actually a divider clock, with the default divider set to 2. l4 then derived from l3 is a fixed factor clock, but the fixed divider is 2 and not 1. Which means the l3 clock is half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch) Signed-off-by:
Rajendra Nayak <rnayak@ti.com> Signed-off-by:
Tero Kristo <t-kristo@ti.com>
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- Jun 26, 2014
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Alexandre Belloni authored
The at91sam9261 doesn't actually have a slow RC oscillator, remove it from the dtsi. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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- Jun 25, 2014
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Alexandre Belloni authored
Define at91sam9261ek's slow crystal frequencies. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Alexandre Belloni authored
mainck (CKGR_MCFR register) is actually using main_osc (CKGR_MOR register). Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Alexandre Belloni authored
ICPLL can only take 0 or 1, it got mixed with OUT which can be in the [0-3] range. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Alexandre Belloni authored
ICPLL can only take 0 or 1, it got mixed with OUT which can be in the [0-3] range. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Rob Herring authored
The versatile dts is missing any clock data. Add the clocks. It is not clear from the documentation where pclk comes from, so for now it is a dummy clock which is sufficient for things to work. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org>
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Rob Herring authored
While not needed for probing, add the "arm,pl180" compatible string for completeness. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Rob Herring authored
Add valid-mask and clear-mask properties to the versatile dts so the platform code doing the same thing can be removed. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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- Jun 24, 2014
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Gregory CLEMENT authored
Wildcards in compatible strings should be avoid. "marvell,armada38x" was recently introduced but was not yet used. The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs and more PCIe slots). So this patch replaces the use of "marvell,armada38x" by the "marvell,armada380" string. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1403533011-21339-1-git-send-email-gregory.clement@free-electrons.com Acked-by:
Andrew Lunn <andrew@lunn.ch> Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
Commit eeb84545 ("ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id") added phy-connection-type properties to ethernet PHY nodes. Actually, the property has to be set for the ethernet port node instead. Fix it by moving the corresponding properties to the correct nodes. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1403555115-13111-1-git-send-email-sebastian.hesselbarth@gmail.com Fixes: eeb84545 : ('ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id') Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- Jun 21, 2014
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Denis Carikli authored
The following commit: 89d7e5c1 mmc: sdhci-esdhc-imx: add runtime pm support has the effect of also disabling the hardware card detect in runtime pm. We switch to GPIO based detection to avoid this issue. This patch is based on: ARM: dts: imx51-babbage: Fix esdhc setup Signed-off-by:
Denis Carikli <denis@eukrea.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Sascha Hauer authored
Since commit 89d7e5c1 (mmc: sdhci-esdhc-imx: add runtime pm support), controller based card detection / write protection is not supported anymore by esdhc driver. Let's use GPIO for CD/WP on esdhc1 instead. While at it, fix cd gpio polarity for esdhc2. This is wrong and currently only works because the imx esdhc driver ignores the polarity. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Marek Vasut authored
Move the display {} node out of the soc {} node . This just aligns the DT with other boards, there is no functional change. Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Marek Vasut authored
The "port" node was misplaced in the original patch, therefore making the LCD dysfunctional on this board. Fix this by moving the "port" DT node into the "display {}" node. Signed-off-by:
Marek Vasut <marex@denx.de> Acked-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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- Jun 19, 2014
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Lee Jones authored
Two reasons for this rename. Firstly, it removes the camel case convention which isn't used by any other platform and secondly it matches the naming convention for the internal kernel, which can become annoying when flipping between the two. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Maxime Coquelin <maxime.coquelin@st.com>
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- Jun 17, 2014
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Ezequiel Garcia authored
The factory bootloader on A385-DB boards expect the ECC strength to be 4 bits over 512 bytes. Hence, we need to specify this in the devicetree, to prevent the kernel from assuming any different ECC scheme. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1400941030-2123-3-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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