- Jul 31, 2014
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Haifeng Yan authored
Rename Hisilicon HI3716 to HIX5HD2 and add dependency on ARCH_HIX5HD2. HiX5HD2 is a SoC with dual Cortex A9 cores for STB market, and original Hi3xxx SoC is for mobile market. To avoid confusing the two types of SoCs and also because of different implementation (SMP, IPs integrated and earlycon config), rename Hi3716 to HIX5HD2 and add ARCH_HIX5HD2. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Jiancheng Xue <jchxue@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> [olof: fixed description typos] Signed-off-by: Olof Johansson <olof@lixom.net>
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Haifeng Yan authored
Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series support both single and dual Cortex-A9 cores. Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx. They are different in implementation such as SMP, IPs integarted and earlycon configure. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Jiancheng Xue <jchxue@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Haojian Zhuang authored
Since multiple ARCH configuration will be appended into mach-hisi directory, add ARCH_HISI as common configuration for different platforms in mach-hisi. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Jul 28, 2014
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Brian Norris authored
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Matt Porter <mporter@linaro.org>
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Marc Carino authored
The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes. This patch adds machine support for the ARM-based Broadcom SoCs. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Matt Porter <mporter@linaro.org>
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Alex Elder authored
Also explicitly set CONFIG_NR_CPUS to 2, limiting it to the most we currently need. Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
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Alex Elder authored
This patch adds SMP support for BCM281XX and BCM21664 family SoCs. This feature is controlled with a distinct config option such that an SMP-enabled multi-v7 binary can be configured to run these SoCs in uniprocessor mode. Since this SMP functionality is used for multiple Broadcom mobile chip families the config option is called ARCH_BCM_MOBILE_SMP (for lack of a better name). On SoCs of this type, the secondary core is not held in reset on power-on. Instead it loops in a ROM-based holding pen. To release it, one must write into a special register a jump address whose low-order bits have been replaced with a secondary core's id, then trigger an event with SEV. On receipt of an event, the ROM code will examine the register's contents, and if the low-order bits match its cpu id, it will clear them and write the value back to the register just prior to jumping to the address specified. The location of the special register is defined in the device tree using a "secondary-boot-reg" property in a node whose "enable-method" matches. Derived from code originally provided by Ray Jui <rjui@broadcom.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
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- Jul 25, 2014
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Arnd Bergmann authored
When building a multiplatform kernel that enables 'ARCH_MVEBU' but none of the individual options under it, we get this link error: arch/arm/mach-mvebu/built-in.o: In function `mvebu_armada375_smp_wa_init': :(.text+0x190): undefined reference to `mvebu_setup_boot_addr_wa' The best solution seems to be to ensure that in this configuration, we don't actually build any of the mvebu code. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/7339332.ZE2mWIdyDh@wuerfel Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Jul 24, 2014
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Gregory CLEMENT authored
Unlike the Armada XP and the Armada 370, this SoC uses a Cortex A9 core. Consequently, the procedure to enter the idle state is different: interaction with the SCU, not disabling snooping, etc. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-16-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
This commit introduces the cpuidle support for Armada 370. The main difference compared to the already supported Armada XP is that the Armada 370 has an issue caused by "a slow exit process from the deep idle state due to heavy L1/L2 cache cleanup operations performed by the BootROM software" (cf errata GL-BootROM-10). To work around this issue, we replace the restart code of the BootROM by some custom code located in an internal SRAM. For this purpose, we use the common function mvebu_boot_addr_wa() introduced in the commit "ARM: mvebu: Add a common function for the boot address work around". The message in case of failure to suspend the system was switched from the warn level to the debug level. Indeed due to the "slow exit process from the deep idle state" in Armada 370, this situation happens quite often. Using the debug level avoids spamming the kernel logs, but still allows to enable it if needed. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-15-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
This driver will be able to manage the cpuidle for more SoCs than just Armada 370 and XP. It will also support Armada 38x and potentially other SoC of the Marvell Armada EBU family. To take this into account, this patch renames the driver and its symbols. It also changes the driver name from cpuidle-armada-370-xp to cpuidle-armada-xp, because separate platform drivers will be registered for the other SoC types. This change must be done simultaneously in the cpuidle driver and in the PMSU code in order to remain bisectable. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lkml.kernel.org/r/1406120453-29291-12-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
The SCU address will be needed in other files than board-v7.c, especially in pmsu.c for cpuidle related activities. So this patch adds a function that allows to retrieve the virtual address at which the SCU has been mapped. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
On some mvebu v7 SoCs (the ones using a Cortex-A9 core and not a PJ4B core), the snoop disabling feature does not exist as the hardware coherency is handled in a different way. Therefore, in preparation to the introduction of the cpuidle support for those SoCs, this commit modifies the mvebu_v7_psmu_idle_prepare() function to take several flags, which allow to decide whether snooping should be disabled, and whether we should use the deep idle mode or not. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
The resume address used by the cpuidle code will not always be the same depending on the SoC. Using a local variable to store the resume address allows to keep the same function for the PM notifier but with a different address. This address will be set during the initialization of the cpuidle logic in pmsu.c. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
In preparation to the addition of the cpuidle support for more SoCs, this patch moves the Armada XP specific initialization to a separate function. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
Most of the function related to the PMSU are not specific to the Armada 370 or Armada XP SoCs. They can also be used for most of the other mvebu ARMv7 SoCs, and will actually be used to support cpuidle on Armada 38x. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
Use the common function mvebu_setup_boot_addr_wa() introduced in the commit "ARM: mvebu: Add a common function for the boot address work around" instead of the dedicated version for Armada 375. This commit also moves the workaround in the system-controller module. Indeed the workaround on 375 is really related to setting the boot address which is done by the system controller. As a bonus we no longer use an harcoded value to access the register storing the boot address. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
On some of the mvebu SoCs and due to internal BootROM issue, the CPU initial jump code must be placed in the SRAM memory of the SoC. In order to achieve this, we have to unmap the BootROM and at some specific location where the BootROM was placed, create a dedicated MBus window for the SRAM. This SRAM is initialized with a few instructions of code that allows to jump to the real secondary CPU boot address. The SRAM used is the Crypto engine one. This work around is currently needed for booting SMP on Armada 375 Z1 and will be needed for cpuidle support on Armada 370. Instead of duplicating the same code, this commit introduces a common function to handle it: mvebu_setup_boot_addr_wa(). Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
Sorting the headers in alphabetic order will help to reduce conflicts when adding new headers later. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
do_armada_370_xp_cpu_suspend() and armada_370_xp_pmsu_idle_prepare(), have been merged into a single function called armada_370_xp_pmsu_idle_enter() by the commit "bbb92284 ARM: mvebu: slightly refactor/rename PMSU idle related functions", in prepare for the introduction of the CPU hotplug support for Armada XP. But for cpuidle the prepare function will be common to all the mvebu SoCs that use the PMSU, while the suspend function will be specific to each SoC. Keeping the prepare function separate will help reducing code duplication while new SoC support is added. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Jul 23, 2014
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Wei Yongjun authored
In case of error, the function clk_get() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Link: https://lkml.kernel.org/r/1406038688-26417-1-git-send-email-weiyj_lk@163.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Romain Perier authored
Adds ability to shutdown all CPUs except the first one (since it might be special for a lot of platforms). It is now possible to use kexec which requires such a feature. Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler flags are for ARMv6, and the following cpu-hotplug change will fail with: /tmp/ccSFxfmI.s:68: Error: selected processor does not support ARM mode `isb ' /tmp/ccSFxfmI.s:74: Error: selected processor does not support ARM mode `isb ' /tmp/ccSFxfmI.s:75: Error: selected processor does not support ARM mode `dsb ' Fix this in a similar manner as in commit 9f0affcf "ARM: mvebu: Fix pmsu compilation when ARMv6 is selected", by specifying ARMv7 flags for platsmp.o. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Pankaj Dubey authored
As exynos_cpuidle_init() and exynos_cpufreq_init() functions have just one line of code for registering platform devices. So we can move them to exynos_dt_machine_init() and remove exynos_cpuidle_init() and exynos_cpufreq_init(). This will help in reducing lines of code in exynos.c, making it more clean. Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Pankaj Dubey authored
Under "arm/mach-exynos" many files are using PMU register offsets. Since we have added support for accessing PMU base address via DT, now we can remove PMU mapping from exynosX_iodesc. Let's convert all these access using iomapped address. This will help us in removing static mapping of PMU base address as well as help in reducing dependency over machine header files. Thus helping for migration of PMU implementation from machine to driver folder which can be reused for ARM64 based SoC. Also as we have removed static mappings from "regs-pmu.h" it does not need map.h anymore. But "platsmp.c" needed this and till now it got included indirectly. So lets move header inclusion of "mach/map.h" from "regs-pmu.h" to "platsmp.c". Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Abhilash Kesavan authored
Turning off a cluster when all 4 cores of the cluster are powered off saves power significantly. Powering off the A15 L2 alone gives around 100mW in savings. Add support for powering off the A15/A7 clusters on exynos5420/5800. The patch enables specific register bits which ensure that: - cluster L2 will be turned on before the first man is powered up. - last man will be turned off before the cluster L2 is turned off. - core is powered down before powering it up. Remove the exynos_cluster_power_control function completely as we can rely on the above mentioned bits rather than polling the cluster power status register. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Lokesh Vutla authored
Add hwmod data for RTC Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Mugunthan V N authored
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC Cc: Rajendra Nayak <rnayak@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Kishon Vijay Abraham I authored
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC. Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Kishon Vijay Abraham I authored
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC. Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro for pcie1 phy and pcie2 phy. Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Roger Quadros authored
This module is needed for the SATA and PCIe PHYs. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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- Jul 22, 2014
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Matthias Brugger authored
The Aquaris5 is a mobile phone based on the MT6589 SoC. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Matthias Brugger authored
This adds a generic devicetree board file and a dtsi for boards based on MT6589 SoCs from Mediatek. Apart from the generic parts (gic, clocks) the only component currently supported are the timers. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Nishanth Menon authored
DMA interrupts are now available in of, and the definitions are duplicates in hwmod. This prevents us from dynamically allocating interrupt resources for dma from devicetree. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Nishanth Menon authored
we have currently 2 DMA drivers that try to co-exist. drivers/dma/omap-dma.c which registers it's own IRQ and is device tree aware and uses arch/arm/plat-omap/dma.c instance created by arch/arm/mach-omap2/dma.c to maintain channel usage (omap_request_dma). Currently both try to register interrupts and mach-omap2/plat-omap dma.c attempts to use the IRQ number registered by hwmod to register it's own interrupt handler. Now, there is no reasonable way of static allocating DMA irq in GIC SPI when we use crossbar. However, since the dma_chan structure is freed as a result of IRQ not being present due to devm allocation, maintaining information of channel by platform code fails at a later point in time when that region of memory is reused. So, if hwmod does not indicate an IRQ number, then, assume that dma-engine will take care of the interrupt handling. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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- Jul 20, 2014
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Krzysztof Kozlowski authored
Fix building of exynos_defconfig with disabled PM_SLEEP: CONFIG_PM_SLEEP=n CONFIG_PM_SLEEP_SMP=n CONFIG_SUSPEND=n by moving functions for power up/down of CPU and cluster to platsmp.c The build error messages: arch/arm/mach-exynos/built-in.o: In function `exynos_boot_secondary': arch/arm/mach-exynos/platsmp.c:111: undefined reference to `exynos_cpu_power_state' arch/arm/mach-exynos/platsmp.c:112: undefined reference to `exynos_cpu_power_up' arch/arm/mach-exynos/platsmp.c:116: undefined reference to `exynos_cpu_power_state' make: *** [vmlinux] Error 1 Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com>,> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Jul 19, 2014
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Tomasz Figa authored
When CPU topology is specified in device tree, cpu_logical_map() does not return core ID anymore, but rather full MPIDR value. This breaks existing calculation of PMU register offsets on Exynos SoCs. This patch fixes the problem by adjusting the code to use only core ID bits of the value returned by cpu_logical_map() to allow CPU topology to be specified in device tree on Exynos SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Tomasz Figa authored
After refactoring suspend/resume, which was last part with dependencies on legacy code, all Kconfig symbols related to Samsung ATAGS support can be deselected and more unused code removed. This includes most of s5p-* code as well, as s5pv210 was their last user. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Tomasz Figa authored
This makes it possible to enable the s5pv210 platform as part of a multiplatform kernel. Also redundant Kconfig options are removed. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Tomasz Figa authored
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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