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  1. Sep 17, 2018
  2. Sep 14, 2018
  3. Sep 13, 2018
    • Andre Naujoks's avatar
      ipv6: Add sockopt IPV6_MULTICAST_ALL analogue to IP_MULTICAST_ALL · 15033f04
      Andre Naujoks authored
      
      
      The socket option will be enabled by default to ensure current behaviour
      is not changed. This is the same for the IPv4 version.
      
      A socket bound to in6addr_any and a specific port will receive all traffic
      on that port. Analogue to IP_MULTICAST_ALL, disable this behaviour, if
      one or more multicast groups were joined (using said socket) and only
      pass on multicast traffic from groups, which were explicitly joined via
      this socket.
      
      Without this option disabled a socket (system even) joined to multiple
      multicast groups is very hard to get right. Filtering by destination
      address has to take place in user space to avoid receiving multicast
      traffic from other multicast groups, which might have traffic on the same
      port.
      
      The extension of the IP_MULTICAST_ALL socketoption to just apply to ipv6,
      too, is not done to avoid changing the behaviour of current applications.
      
      Signed-off-by: default avatarAndre Naujoks <nautsch2@gmail.com>
      Acked-By: default avatarYOSHIFUJI Hideaki <yoshfuji@linux-ipv6.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      15033f04
    • David S. Miller's avatar
      Merge branch 'Lantiq-Intel-vrx200-support' · d03790f5
      David S. Miller authored
      
      
      Hauke Mehrtens says:
      
      ====================
      Add support for Lantiq / Intel vrx200 network
      
      This adds basic support for the GSWIP (Gigabit Switch) found in the
      VRX200 SoC.
      There are different versions of this IP core used in different SoCs, but
      this driver was currently only tested on the VRX200 SoC line, for other
      SoCs this driver probably need some adoptions to work.
      
      I also plan to add Layer 2 offloading to the DSA driver and later also
      layer 3 offloading which is supported by the PPE HW block.
      
      All these patches should go through the net-next tree.
      
      This depends on the patch "MIPS: lantiq: dma: add dev pointer" which
      should go into 4.19.
      
      Changes since:
      v2:
       * Send patch "MIPS: lantiq: dma: add dev pointer" separately
       * all: removed return in register write functions
       * switch: uses phylink
       * switch: uses hardware MDIO auto polling
       * switch: use usleep_range() in MDIO busy check
       * switch: configure MDIO bus to 2.5 MHz
       * switch: disable xMII link when it is not used
       * Ethernet: use NAPI for TX cleanups
       * Ethernet: enable clock in open callback
       * Ethernet: improve skb allocation
       * Ethernet: use net_dev->stats
      
      v1:
       * Add "MIPS: lantiq: dma: add dev pointer"
       * checkpatch fixes a all patches
       * Added binding documentation
       * use readx_poll_timeout function and ETIMEOUT error code
       * integrate GPHY firmware loading into DSA driver
       * renamed to NET_DSA_LANTIQ_GSWIP
       * removed some needed casts
       * added of_device_id.data information about the detected switch
       * fixed John's email address
      ====================
      
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d03790f5
    • Hauke Mehrtens's avatar
      net: dsa: Add Lantiq / Intel DSA driver for vrx200 · 14fceff4
      Hauke Mehrtens authored
      
      
      This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC.
      This switch is integrated in the DSL SoC, this SoC uses a GSWIP version
      2.1, there are other SoCs using different versions of this IP block, but
      this driver was only tested with the version found in the VRX200.
      Currently only the basic features are implemented which will forward all
      packages to the CPU and let the CPU do the forwarding. The hardware also
      support Layer 2 offloading which is not yet implemented in this driver.
      
      The GPHY FW loaded is now done by this driver and not any more by the
      separate driver in drivers/soc/lantiq/gphy.c, I will remove this driver
      is a separate patch. to make use of the GPHY this switch driver is
      needed anyway. Other SoCs have more embedded GPHYs so this driver should
      support a variable number of GPHYs. After the firmware was loaded the
      GPHY can be probed on the MDIO bus and it behaves like an external GPHY,
      without the firmware it can not be probed on the MDIO bus.
      
      The clock names in the sysctrl.c file have to be changed because the
      clocks are now used by a different driver. This should be cleaned up and
      a real common clock driver should provide the clocks instead.
      
      Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      14fceff4
    • Hauke Mehrtens's avatar
      dt-bindings: net: dsa: Add lantiq, xrx200-gswip DT bindings · 86ce2bc7
      Hauke Mehrtens authored
      
      
      This adds the binding for the GSWIP (Gigabit switch) core found in the
      xrx200 / VR9 Lantiq / Intel SoC.
      
      This part takes care of the switch, MDIO bus, and loading the FW into
      the embedded GPHYs.
      
      Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
      Cc: devicetree@vger.kernel.org
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      86ce2bc7
    • Hauke Mehrtens's avatar
      net: lantiq: Add Lantiq / Intel VRX200 Ethernet driver · fe1a5642
      Hauke Mehrtens authored
      
      
      This drives the PMAC between the GSWIP Switch and the CPU in the VRX200
      SoC. This is currently only the very basic version of the Ethernet
      driver.
      
      When the DMA channel is activated we receive some packets which were
      send to the SoC while it was still in U-Boot, these packets have the
      wrong header. Resetting the IP cores did not work so we read out the
      extra packets at the beginning and discard them.
      
      This also adapts the clock code in sysctrl.c to use the default name of
      the device node so that the driver gets the correct clock. sysctrl.c
      should be replaced with a proper common clock driver later.
      
      Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      fe1a5642
    • Hauke Mehrtens's avatar
      dt-bindings: net: Add lantiq, xrx200-net DT bindings · 839790e8
      Hauke Mehrtens authored
      
      
      This adds the binding for the PMAC core between the CPU and the GSWIP
      switch found on the xrx200 / VR9 Lantiq / Intel SoC.
      
      Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
      Cc: devicetree@vger.kernel.org
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      839790e8
    • Hauke Mehrtens's avatar
      net: dsa: Add Lantiq / Intel GSWIP tag support · 79691192
      Hauke Mehrtens authored
      
      
      This handles the tag added by the PMAC on the VRX200 SoC line.
      
      The GSWIP uses internally a GSWIP special tag which is located after the
      Ethernet header. The PMAC which connects the GSWIP to the CPU converts
      this special tag used by the GSWIP into the PMAC special tag which is
      added in front of the Ethernet header.
      
      This was tested with GSWIP 2.1 found in the VRX200 SoCs, other GSWIP
      versions use slightly different PMAC special tags.
      
      Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      79691192