- Feb 14, 2018
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Chris Zhong authored
Add a node for the cdn DP controller which is embedded in the rk3399 SoC. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> [fixed whitespaces instead of tabs, dropped unnecessary address+size-cells and fixed the number of interrupt cells] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Feb 12, 2018
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Klaus Goger authored
Add pin definition for I2S0 if used as a 2-channel only bus. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shunqian Zheng authored
There are three pins can act as cif test clock for rk3399. They're sourced from 24M and output 24M by default and some boards may use them as camera 24M xvclk. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Dec 17, 2017
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Enric Balletbo i Serra authored
Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enric Balletbo i Serra authored
After commit '06c47e62 usb: dwc3: of-simple: Add support to get resets for the device' you can add the reset property to the dwc3 node, the reset is required for the controller to work properly, otherwise bind / unbind stress testing of the USB controller on rk3399 we'd often end up with lots of failures that looked like this: phy phy-ff800000.phy.9: phy poweron failed --> -110 dwc3 fe900000.dwc3: failed to initialize core dwc3: probe of fe900000.dwc3 failed with error -110 Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enric Balletbo i Serra authored
The aclk_usb3 must be enabled to support USB3 for rk3399. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Enric Balletbo i Serra authored
Add the usb3 power-domain, its qos area and assign it to the usb device node. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Dec 04, 2017
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Nickey Yang authored
We might include additional ports in derivative device trees, so the 'port' node should have an address, and the parent 'ports' node needs /#{addres,size}-cells. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Nickey Yang authored
This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
We've documented this one already, but we didn't add it to the DTSI yet. Suggested-by: Nickey Yang <nickey.yang@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Oct 18, 2017
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Jacob Chen authored
This patch add the RGA dt config of RK3399 SoC. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Oct 15, 2017
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Pierre-Hugues Husson authored
Add the HDMI CEC controller main clock coming from the CRU. Signed-off-by: Pierre-Hugues Husson <phh@phh.me> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Sep 26, 2017
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Nickey Yang authored
The clk of grf must be enabled before writing grf register for rk3399. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> [the grf clock is already part of the binding since march 2017] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Sep 20, 2017
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Nickey Yang authored
There is a further gate in between the mipidphy reference clock and the actual ref-clock input to the dsi host, making the clock hirarchy look like clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll Fix the clock reference so that the whole clock subtree gets enabled when the dsi host needs it. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> [amended commit message] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 30, 2017
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Shawn Lin authored
Convert all RK3399 platforms to use per-lane PHY model in order to save more power by idling unused lane(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
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- Aug 22, 2017
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Simon Xue authored
Add VPU/VDEC/IEP/ISP0/ISP1 iommu nodes Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 19, 2017
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Kever Yang authored
We need to init vop aclk and hclk incase the U-Boot does not do the initialize. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 18, 2017
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William Wu authored
RK3399 USB DWC3 controller has a issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. It's because that the inter-packet delay between the SSPLIT token to SETUP token is about 566ns, more then the USB spec requirement. This patch adds a quirk "snps,dis-tx-ipgap-linecheck-quirk" to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 06, 2017
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Jacob Chen authored
Add an hdmi node, and also add hdmi endpoints to vopb and vopl output port nodes. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Jacob Chen authored
Add an mipi node, and also add mipi endpoints to vopb and vopl output port nodes. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Yakir Yang authored
Add an edp node, and also add edp endpoints to vopb and vopl output port nodes. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Elaine Zhang authored
1. add pd node for RK3399 Soc 2. create power domain tree 3. add qos node for domain Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Mark Yao authored
Add devicetree nodes for rk3399 VOP (Video Output Processors), and the top level display-subsystem root node. Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the VOPs' output ports. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 01, 2017
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Caesar Wang authored
This patch updates the dynamic-power-coefficient for big cluster on rk3399 SoCs. The dynamic power consumption of the CPU is proportional to the square of the Voltage (V) and the clock frequency (f). The coefficient is used to calculate the dynamic power as below - Pdyn = dynamic-power-coefficient * V^2 * f Where Voltage is in uV, frequency is in MHz. As the following is the tested data on rk3399's big cluster. frequency(MHz) Voltage(V) Current(mA) Dynamic-power-coefficient 24 0.8 15 48 0.8 23 ~417 96 0.8 40 ~443 216 0.8 82 ~438 312 0.8 115 ~430 408 0.8 150 ~455 So the dynamic-power-coefficient average value is about 436. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jul 23, 2017
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Shawn Lin authored
Kill these two pinctrl reference totally from rk3399 as it never work indeed. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Caesar Wang authored
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq opp table. RK3399 and RK3399-OP1 SoCs have a different recommendation table with gpu opp. Also, the ARM's mali driver found on https://developer.arm.com/products/software/mali-drivers/midgard-kernel . Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jul 16, 2017
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Caesar Wang authored
The SdioAudio power domain includes the i2s/spdif/spi5/sdio. So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order to save more power consumption. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
Provide the dynamic power coefficient of the big and little CPU clusters. These numbers are currently in use on the Samsung Chromebook Plus ("Kevin"). The power allocator thermal governor doesn't know how to do anything if it doesn't get power parameters from its cooling devices (in this case, CPUfreq). So this effectively enables the power-allocator governor. Signed-off-by: Brian Norris <briannorris@chromium.org> [set the property in each core node] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Klaus Goger authored
replace all occurrences of sdmcc with sdmmc in the arm64 rockchip devicetree files. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- May 30, 2017
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Heiko Stuebner authored
This is used by bootloaders to override the mac address in the devicetree if needed. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- May 23, 2017
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Shawn Lin authored
Make full use of 32 regions and increase IORESOURCE_MEM_64 so that we could have more chance to support PCIe switch with more endpoints attached to our RC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
In order to support multiple hierarchy of PCIe buses, for instance, PCIe switch, we need to extent bus-ranges to as max as possible. We have 32 regions and could support up to 31 buses except bus 0 for our root bridge. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Kever Yang authored
Add pinctrl for sdio, sdmmc, pcie, spdif, hdmi. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Kever Yang authored
Add qos setting reg for some peripheral like sd, usb, pcie. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Mar 23, 2017
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Shawn Lin authored
It's suggested to fix the domain number for all PCIe host bridges or not set it at all. However, if we don't fix it, the domain number will keep increasing ever when doing unbind/bind test, which makes the bus tree of lspci introduce pointless domain hierarchy. More investigation shows the domain number allocater of PCI doesn't consider the conflict of domain number if we have more than one PCIe port belonging to different domains. So once unbinding/binding one of them and keep others would going to overflow the domain number so that finally it will share the same domain as others, but actually it shouldn't. We should fix the domain number for PCIe or invent new indexing ID mechanisms. However it isn't worth inventing new indexing ID mechanisms personlly, Just look at how other Root Complex drivers did, for instance, broadcom and qualcomm, it seems fixing the domain number was more popular. So this patch gonna fix the domain number of PCIe for rk3399. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Mar 22, 2017
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Heiko Stuebner authored
dw-mmc got its reset-properties specified, so add the softresets for it on the rk3399. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
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Brian Norris authored
Add the dwc3 usb needed node information for rk3399. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Mar 06, 2017
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Brian Norris authored
f8000000 is less than all the other (top-level) unit addresses. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jan 14, 2017
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Xing Zheng authored
The structure rockchip_clk_provider needs to refer the GRF regmap in somewhere, if the CRU node has not "rockchip,grf" property, calling syscon_regmap_lookup_by_phandle will return an invalid GRF regmap, and the MUXGRF type clock will be not supported. Therefore, we need to add them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Jan 13, 2017
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Shawn Lin authored
Per the discussion of bug fix[1], we now actually leaves the default clock choice for pcie phy is derived from 24MHz OSC to guarantee the least BER. So let's add aspm-no-l0s here and folks could delete this property from their dts. [1] https://patchwork.kernel.org/patch/9470519/ Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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