- Feb 20, 2019
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Ben Skeggs authored
This uses HMM to mirror a process' CPU page tables into a channel's page tables, and keep them synchronised so that both the CPU and GPU are able to access the same memory at the same virtual address. While this code also supports Volta/Turing, it's only enabled for Pascal GPUs currently due to channel recovery being unreliable right now on the later GPUs. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
For a channel to make use of SVM features, it requires a different GPU MMU configuration than we would normally use, which is not desirable to switch to unless a client is actively going to use SVM. In order to supporting SVM without more extensive changes to the userspace interfaces, the SVM_INIT ioctl needs to replace the previous configuration safely. The only way we can currently do this safely, accounting for some unlikely failure conditions, is to allocate the new VMM without destroying the last one, and prioritising the SVM-enabled configuration in the code that cares. This will get cleaned up again further down the track. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
This nvclass exposes the replayable fault buffer, which will be used by SVM to manage GPU page faults. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
This nvclass exposes the replayable fault buffer, which will be used by SVM to manage GPU page faults. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Some GPU units are capable of supporting "replayable" page faults, where the execution unit will wait for SW to fixup GPU page tables rather than triggering a channel-fatal fault. This feature isn't useful (it's harmful, even) unless something like HMM is being used to manage events appearing in the replayable fault buffer, so, it's disabled by default. This commit allows a client to request it be enabled. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Host methods exist to do at least some of what we need, but we are not currently pushing replay/cancels through a channel like UVM does as it's not clear whether it's necessary in our case (UVM also updates PTEs with the GPU). UVM also pushes a software method for fault cancels on Pascal, seemingly because the host methods don't appear to be sufficient. If/when we want to push the replay/cancel on the GPU, we can re-purpose the cancellation code here to implement that swmthd. Keep it simple for now, until we figure out exactly what we need here. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
This provides a somewhat more direct method of manipulating the GPU page tables, which will be required to support SVM. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
This will be used to support a privileged client providing PTEs directly, without a memory object to use as a reference. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
NVKM is currently responsible for managing the allocation of a client's GPU address-space, but there's various use-cases (ie. HMM address-space mirroring) where giving a client more direct control is desirable. This commit allows for a VMM to be created where the area allocated for NVKM is limited to a client-specified window, the remainder of address- space is controlled directly by the client. Leaving a window is necessary to support various internal requirements, but also to support existing allocation interfaces as not all of the HW is capable of working with a HMM allocation. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
MMU will need access to this info. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
MMU will need access to these. v2. Apply fix from Rhys Kidd to send correct FECS method for STOP_CTXSW. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Colin Ian King authored
There are a few statements that are indented incorrectly. Fix these. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
It appears that Pascal and newer need something different. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Will want to reuse this for fault replay/cancellation swmthds. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Future changes will want to add some additional things here, keep them grouped together. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Makes the code somewhat less magic. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
This is already done during golden context creation. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Makes the code somewhat less magic. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Makes the code somewhat less magic. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Makes the code somewhat less magic. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Makes the code somewhat less magic. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Makes the code somewhat less magic. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
There's no need to avoid using copy engines if gr init fails for some reason (usually missing FW, or incomplete bring-up). It's not terribly useful for an end-user, but it'll slightly speed up suspend/resume when saving fb contents, and allow for host/ce code to be validated. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
It has no relevance to the atomic path used by newer GPUs. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
It has no relevance to the atomic path used by newer GPUs. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Swapped order of functions in dispnv04 to allow this, but no code changes. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Some of the pre-NV50 depends on SW methods to implement synchronisation for page flips, and we want to move this setup out of common code, thus we require the channel to have been allocation before display init. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
We also change the error strings to match NVIDIA's naming. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
As I currently understand it, this is related to features we have no support for as of yet. In theory, this change should be a noop, just without the warning. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Required for ACR. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Turing has its SEC2 instance in an alternate location, and this avoids needing to duplicate the code here for it. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Required to run VPR scrubber binary as part of secboot. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Turing has its NVDEC instances in an alternate location. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
We need this for Turing ACR, but it's present from Volta onwards. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
So we're able to connect fault/interrupt handling to the GSP subdev. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Will be using this in upcoming changes to avoid the need for entirely new subdevs to deal with Turing register moves. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Exact meaning of the acronym is unknown, but we need this for Turing ACR. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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