- Jan 30, 2020
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Bjorn Helgaas authored
- Fix checking of pm_runtime_get_sync() return value (David Engraf) - Fix AFI_PEX2_CTRL reg offset for Tegra30 (Marcel Ziswiler) * remotes/lorenzo/pci/tegra: PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30 PCI: tegra: Fix return value check of pm_runtime_get_sync()
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Bjorn Helgaas authored
- Add DT clock/reset info for SDM845 PCIe controller (Bjorn Andersson) - Add support for SDM845 PCIe controller to the qcom driver (Bjorn Andersson) * remotes/lorenzo/pci/qcom: PCI: qcom: Add support for SDM845 PCIe controller dt-bindings: PCI: qcom: Add support for SDM845 PCIe
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Bjorn Helgaas authored
- Fix "EXYNOS" typographical styling (Krzysztof Kozlowski) - Update MAINTAINERS with Andrew Murray's email address (Andrew Murray) * remotes/lorenzo/pci/misc: MAINTAINERS: Update my email address PCI: exynos: Rename Exynos to lowercase
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Bjorn Helgaas authored
- Fix link training so we can do it more than once (Yurii Monakov) - Fix keystone outbound window mapping (Yurii Monakov) - Fix error handling when DT lacks "num-viewport" (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: PCI: keystone: Fix error handling when "num-viewport" DT property is not populated PCI: keystone: Fix outbound region mapping PCI: keystone: Fix link training retries initiation
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Bjorn Helgaas authored
- Add intel-gw driver for PCIe host controller on Intel Gateway SoC (Dilip Kota) - Use shared DesignWare helpers to configure Fast Training Sequence (FTS) in artpec6 (Dilip Kota) * remotes/lorenzo/pci/dwc: PCI: artpec6: Configure FTS with dwc helper function PCI: dwc: intel: PCIe RC controller driver dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
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Bjorn Helgaas authored
- Add brcmstb PCIe bindings for Raspberry Pi 4 (Jim Quinlan) - Add Broadcom STB PCIe host controller driver (Jim Quinlan) - Add MSI support for Broadcom STB PCIe host controller driver (Jim Quinlan) * remotes/lorenzo/pci/brcmstb: PCI: brcmstb: Add MSI support PCI: brcmstb: Add Broadcom STB PCIe host controller driver dt-bindings: PCI: Add bindings for brcmstb's PCIe device
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Bjorn Helgaas authored
- Save VMD's pci_dev in x86 struct pci_sysdata (Jon Derrick) - Add pci_real_dma_dev() for DMA aliases not on the same bus as requester (Jon Derrick) - Add IOMMU mappings for pci_real_dma_dev() (Jon Derrick) - Remove IOMMU sanity checks for VMD devices (Jon Derrick) - Remove VMD dma_map_ops overrides (Jon Derrick) - Remove unused X86_DEV_DMA_OPS (Christoph Hellwig) - Add VMD device IDs that need bus restriction mode (Sushma Kalakota) * pci/host-vmd: PCI: vmd: Add two VMD Device IDs x86/PCI: Remove X86_DEV_DMA_OPS PCI: vmd: Remove dma_map_ops overrides iommu/vt-d: Remove VMD child device sanity check iommu/vt-d: Use pci_real_dma_dev() for mapping PCI: Introduce pci_real_dma_dev() x86/PCI: Expose VMD's pci_dev in struct pci_sysdata x86/PCI: Add to_pci_sysdata() helper
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Bjorn Helgaas authored
- Fix memory leak in pci_iov_add_virtfn() (Navid Emamdoost) - Extend pci_add_dma_alias() so it can add a range of aliases (James Sewart) - Add DMA aliases for PLX PEX NTB (James Sewart) * pci/virtualization: PCI: Add DMA alias quirk for PLX PEX NTB PCI: Add nr_devfns parameter to pci_add_dma_alias() PCI: Fix pci_add_dma_alias() bitmask size PCI/IOV: Fix memory leak in pci_iov_add_virtfn()
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Bjorn Helgaas authored
- Support 64-bit addressing for both streaming and coherent DMA (Wesley Sheng) - Read vep_vector_number with 16-bit, not 32-bit read (Logan Gunthorpe) - Add Intercomm Notify and Upstream Error Containment support (Logan Gunthorpe) - Remove redundant valid PFF number count (Wesley Sheng) - Avoid unnecessary CSR read in ISR (Wesley Sheng) - Rename Gen3-specific constants (Logan Gunthorpe) - Rework infrastructure to support Gen3- and Gen4-specific code (Logan Gunthorpe) - Add Gen4 system info register support (Logan Gunthorpe) - Add Gen4 flash information interface support (Kelvin Cao) - Add Gen4 MRPC GAS access permission check (Kelvin Cao) * pci/switchtec: PCI/switchtec: Add Gen4 device IDs PCI/switchtec: Add Gen4 MRPC GAS access permission check PCI/switchtec: Add Gen4 flash information interface support PCI/switchtec: Add Gen4 system info register support PCI/switchtec: Separate Gen3 register structures into unions PCI/switchtec: Factor out Gen3 ioctl_flash_part_info() PCI/switchtec: Add 'generation' variable PCI/switchtec: Rename generation-specific constants PCI/switchtec: Move check event ID from mask_event() to switchtec_event_isr() PCI/switchtec: Remove redundant valid PFF number count PCI/switchtec: Add support for Intercomm Notify and Upstream Error Containment PCI/switchtec: Fix vep_vector_number ioread width PCI/switchtec: Use dma_set_mask_and_coherent()
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Bjorn Helgaas authored
- Clear only bridge windows (not BARs) while assigning bus resources (Logan Gunthorpe) - Improve resource assignment for deep hotplug hierarchies, e.g., Thunderbolt (Nicholas Johnson) * pci/resource: PCI: Allow adjust_bridge_window() to shrink resource if necessary PCI: Set resource size directly in adjust_bridge_window() PCI: Rename extend_bridge_window() to adjust_bridge_window() PCI: Rename extend_bridge_window() parameter PCI: Consider alignment of hot-added bridges when assigning resources PCI: Remove local variable usage in pci_bus_distribute_available_resources() PCI: Pass size + alignment to pci_bus_distribute_available_resources() PCI: Rename variables PCI: Remove unnecessary braces PCI: Don't disable bridge BARs when assigning bus resources
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Bjorn Helgaas authored
- Print config space before suspend for debugging (Chen Yu) * pci/pm: PCI/PM: Print config space of devices before suspend
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Bjorn Helgaas authored
- Add Intel SkyLake-E to the whitelist of host bridges that support peer-to-peer DMA (Armen Baloyan) * pci/p2pdma: PCI/P2PDMA: Add Intel SkyLake-E to the whitelist
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Bjorn Helgaas authored
- Fix Broadcom iProc quirk so it's applied regardless of whether the iproc driver is built-in or a module (Wei Liu) - Add extra delay when resuming AMD Ryzen5/7 XHCI controllers from D3hot so they work after resume from runtime suspend or suspend-to-idle (Daniel Drake) - Fix pci_alloc_irq_vectors() function name typo in docs (Zenghui Yu) * pci/misc: Documentation: PCI: Fix pci_alloc_irq_vectors() function name typo PCI: Increase D3 delay for AMD Ryzen5/7 XHCI controllers PCI: Add generic quirk for increasing D3hot delay PCI: iproc: Apply quirk_paxc_bridge() for module as well as built-in
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Bjorn Helgaas authored
- Log a message to identify the device that caused AER/DPC recovery to fail (Yicong Yang) - Initialize aer_fifo before use (Dongdong Liu) * pci/aer: PCI/AER: Initialize aer_fifo PCI/AER: Factor message prefixes with dev_fmt() PCI/AER: Log which device prevents error recovery
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Nicholas Johnson authored
Remove checks for resource size in adjust_bridge_window(). This is necessary to allow pci_bus_distribute_available_resources() to function when the kernel parameter "pci=hpmemsize=nn[KMG]" is used to allocate resources. Because the kernel parameter sets the size of all hotplug bridges to be the same, there are problems when nested hotplug bridges are encountered. Fitting a downstream hotplug bridge with size X and normal bridges with non-zero size Y into parent hotplug bridge with size X is impossible, and hence the downstream hotplug bridge needs to shrink to fit into its parent. Add check for if bridge is extended or shrunken and reflect that in the call to pci_dbg(). Reset the resource if its new size is zero (if we have run out of a bridge window resource) to prevent the PCI resource assignment code from attempting to assign a zero-sized resource. Link: https://lore.kernel.org/r/PSXP216MB0438D3E2CFE64EBAA32AF691803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Nicholas Johnson authored
Change adjust_bridge_window() to set resource size directly instead of using additional resource lists. Because additional resource lists are optional resources, any algorithm that requires guaranteed allocation that uses them cannot be guaranteed to work. Remove the resource from add_list, as a zero-sized additional resource is redundant. Update comment in pci_bus_distribute_available_resources() to reflect the above changes. Link: https://lore.kernel.org/r/PSXP216MB04386BA48874B56BC5CB0292803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Nicholas Johnson authored
Rename extend_bridge_window() to adjust_bridge_window() to prepare for the fact that the window will be able to shrink. No functional change intended. Link: https://lore.kernel.org/r/PSXP216MB0438C47B3473D0C9DE531F18803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Nicholas Johnson authored
In extend_bridge_window(), change "available" parameter name to "new_size". This makes more sense as this parameter represents the new size for the window. No functional change intended. Link: https://lore.kernel.org/r/PSXP216MB043853617ECA4118C472A417803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Nicholas Johnson authored
Change pci_bus_distribute_available_resources() to better handle bridges with different resource alignment requirements. The arguments io, mmio and mmio_pref represent the start and end addresses of resource, into which we must fit the current bridge window. The steps taken by pci_bus_distribute_available_resources(): - For io, mmio and mmio_pref, increase .start to align with the alignment of the current bridge window (otherwise the current bridge window may not fit within the available range). - For io, mmio and mmio_pref, adjust the current bridge window to the size after the above. - Count the number of hotplug bridges and normal bridges on this bus. - If the total number of bridges is one, give that bridge all of the resources and return. - If there are no hotplug bridges, return. - For io, mmio and mmio_pref, increase .start by the amount required for each bridge resource on the bus for non hotplug bridges, giving extra room to make up for alignment of those resources. - For io, mmio and mmio_pref, calculate the resource size per hotplug bridge which is available after the previous steps. - For io, mmio and mmio_pref, distribute the resources to each hotplug bridge, with the sizes calculated above. The motivation for fixing this is enabling devices that require greater than 1MB alignment. This fixes the case where the user hot-adds devices with BAR alignment >1MB and Linux fails to assign resources to it. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199581 Link: https://lore.kernel.org/r/PSXP216MB0438C2BFD0FD3691ED9C83F4803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Nicholas Johnson authored
In pci_bus_distribute_available_resources(), use resource_size() rather than the local available_io, etc. No functional change intended; this just makes the preceding patch smaller. [bhelgaas: extracted from https://lore.kernel.org/r/PSXP216MB0438587C47CBEDF365B1EA27803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM ] Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Nicholas Johnson authored
Change pci_bus_distribute_available_resources() arguments from resource_size_t to struct resource to add more information required to get the alignment correct for bridge windows with alignment >1M. We require (size, alignment), instead of just (size) which is what is currently available. The change from resource_size_t to struct resource does just that. Note that the struct resource arguments are passed by value and not by reference. We do not want to pass by reference and change the resource size of the parent bridge window. We only want the size information. No functional change intended. Link: https://lore.kernel.org/r/PSXP216MB0438587C47CBEDF365B1EA27803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM [bhelgaas: split parts to other patches to reduce the size of this one] Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Nicholas Johnson authored
In pci_bus_distribute_available_resources(), rename: io => io_per_hp mmio => mmio_per_hp mmio_pref => mmio_pref_per_hp No functional change; this is just to make a subsequent patch smaller. [bhelgaas: extracted from https://lore.kernel.org/r/PSXP216MB0438587C47CBEDF365B1EA27803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM ] Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Sushma Kalakota authored
Add new VMD device IDs that require the bus restriction mode. Signed-off-by: Sushma Kalakota <sushmax.kalakota@intel.com> Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Nicholas Johnson authored
Remove unnecessary braces in pci_bus_distribute_available_resources(). No functional changes. Link: https://lore.kernel.org/r/PSXP216MB0438061CB4442460BB92A75F803C0@PSXP216MB0438.KORP216.PROD.OUTLOOK.COM Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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- Jan 28, 2020
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Jim Quinlan authored
This adds MSI support to the Broadcom STB PCIe host controller. The MSI controller is physically located within the PCIe block, however, there is no reason why the MSI controller could not be moved elsewhere in the future. MSIX is not supported by the HW. Since the internal Brcmstb MSI controller is intertwined with the PCIe controller, it is not its own platform device but rather part of the PCIe platform device. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
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Jim Quinlan authored
This adds a basic driver for Broadcom's STB PCIe controller, for now aimed at Raspberry Pi 4's SoC, bcm2711. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> [lorenzo.pieralisi@arm.com: updated brcm_pcie_get_rc_bar2_size_and_offset()according to https://lore.kernel.org/linux-pci/be8ddb33a7360af1815cf686f77f3f0913d02be3.camel@suse.de ] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
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- Jan 25, 2020
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Christoph Hellwig authored
There are no users of X86_DEV_DMA_OPS left, so remove the code. Link: https://lore.kernel.org/r/1579613871-301529-8-git-send-email-jonathan.derrick@intel.com Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jon Derrick <jonathan.derrick@intel.com>
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Jon Derrick authored
Devices on the VMD domain use the VMD endpoint's requester ID and have been relying on the VMD endpoint's DMA operations. The problem with this was that VMD domain devices would use the VMD endpoint's attributes when doing DMA and IOMMU mapping. We can be smarter about this by only using the VMD endpoint when mapping and providing the correct child device's attributes during DMA operations. Remove the dma_map_ops redirect. Link: https://lore.kernel.org/r/1579613871-301529-7-git-send-email-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Jon Derrick authored
Remove the sanity check required for VMD child devices. The new pci_real_dma_dev() DMA alias mechanism places them in the same IOMMU group as the VMD endpoint. Assignment of the group would require assigning the VMD endpoint, where unbinding the VMD endpoint removes the child device domain from the hierarchy. Link: https://lore.kernel.org/r/1579613871-301529-6-git-send-email-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
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Jon Derrick authored
The PCI device may have a DMA requester on another bus, such as VMD subdevices needing to use the VMD endpoint. This case requires the real DMA device for the IOMMU mapping, so use pci_real_dma_dev() to find that device. Link: https://lore.kernel.org/r/1579613871-301529-5-git-send-email-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
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Jon Derrick authored
The current DMA alias implementation requires the aliased device be on the same PCI bus as the requester ID. Add an arch-specific mechanism to point to another PCI device when doing mapping and PCI DMA alias search. The default case returns the actual device. Link: https://lore.kernel.org/r/1579613871-301529-4-git-send-email-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Christoph Hellwig <hch@lst.de>
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Jon Derrick authored
Expose VMD's pci_dev pointer in struct pci_sysdata. This will be used indirectly by intel-iommu.c to find the correct domain. Link: https://lore.kernel.org/r/1579613871-301529-3-git-send-email-jonathan.derrick@intel.com [bhelgaas: commit log] Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Christoph Hellwig <hch@lst.de>
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Christoph Hellwig authored
Various helpers need the pci_sysdata just to dereference a single field in it. Add a little helper that returns the properly typed sysdata pointer to require a little less boilerplate code. [jonathan.derrick: to_pci_sysdata const argument] Link: https://lore.kernel.org/r/1579613871-301529-2-git-send-email-jonathan.derrick@intel.com Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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- Jan 24, 2020
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Dongdong Liu authored
Previously we did not call INIT_KFIFO() for aer_fifo. This leads to kfifo_put() sometimes returning 0 (queue full) when in fact it is not. It is easy to reproduce the problem by using aer-inject: $ aer-inject -s :82:00.0 multiple-corr-nonfatal The content of the multiple-corr-nonfatal file is as below: AER COR RCVR HL 0 1 2 3 AER UNCOR POISON_TLP HL 4 5 6 7 Fixes: 27c1ce8b ("PCI/AER: Use kfifo for tracking events instead of reimplementing it") Link: https://lore.kernel.org/r/1579767991-103898-1-git-send-email-liudongdong3@huawei.com Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Bjorn Helgaas authored
Define dev_fmt() with the common prefix of log messages so we don't have to repeat it in every printk. No functional change intended. Link: https://lore.kernel.org/r/20191213225709.GA213811@google.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Yicong Yang authored
PCI error recovery will fail if any device under the Root Port doesn't have an error_detected callback. Currently only the failure result is printed, which is not enough to identify the driver that lacks the callback. Log a message to identify the device with no error_detected callback. [bhelgaas: tweak log message] Link: https://lore.kernel.org/r/1576237474-32021-1-git-send-email-yangyicong@hisilicon.com Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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- Jan 22, 2020
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Andrew Murray authored
I will lose access to my @arm.com email address next week, so let's update the MAINTAINERS file and map it correctly in .mailmap Signed-off-by: Andrew Murray <andrew.murray@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Kishon Vijay Abraham I authored
Fix error handling when "num-viewport" DT property is not populated. Fixes: 23284ad6 ("PCI: keystone: Add support for PCIe EP in AM654x Platforms") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org # v5.2+
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- Jan 16, 2020
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Kelvin Cao authored
Now that Gen4 is properly supported, advertise support in the module's device ID table and add the same IDs to the list of switchtec quirks. [logang@deltatee.com: add commit message and quirk IDs] Link: https://lore.kernel.org/r/20200115035648.2578-8-logang@deltatee.com Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Kelvin Cao authored
Gen4 hardware provides new MRPC commands to read and write directly from any address in the PCI BAR (which Microsemi refers to as GAS). Since accessing BARs can be dangerous and break the driver, we don't want unprivileged users to have this ability. Therefore, require CAP_SYS_ADMIN for the local and remote GAS access MRPC commands. Privileged processes will already have access to the BAR through the sysfs resource file so this doesn't give userspace any capabilities it didn't already have. [logang@deltatee.com: rework commit message] Link: https://lore.kernel.org/r/20200106190337.2428-11-logang@deltatee.com Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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