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  1. Sep 02, 2023
    • Pawel Zmarzly's avatar
      ata: libata-core: Disable NCQ_TRIM on Micron 1100 drives · 27fd0710
      Pawel Zmarzly authored
      
      
      Micron 1100 drives lock up when encountering queued TRIM command. It is
      a quite old hardware series, for past years we have been running our
      machines with these drives using libata.force=noncqtrim.
      
      [Damien] Move the "Crucial_CT*M500*" entry to keep Micron and Crucial
      entries together.
      
      Signed-off-by: default avatarPawel Zmarzly <pzmarzly@meta.com>
      Signed-off-by: default avatarDamien Le Moal <dlemoal@kernel.org>
      27fd0710
    • Werner Fischer's avatar
      ata: ahci: Add Elkhart Lake AHCI controller · 2a2df98e
      Werner Fischer authored
      
      
      Elkhart Lake is the successor of Apollo Lake and Gemini Lake. These
      CPUs and their PCHs are used in mobile and embedded environments.
      
      With this patch I suggest that Elkhart Lake SATA controllers [1] should
      use the default LPM policy for mobile chipsets.
      The disadvantage of missing hot-plug support with this setting should
      not be an issue, as those CPUs are used in embedded environments and
      not in servers with hot-plug backplanes.
      
      We discovered that the Elkhart Lake SATA controllers have been missing
      in ahci.c after a customer reported the throttling of his SATA SSD
      after a short period of higher I/O. We determined the high temperature
      of the SSD controller in idle mode as the root cause for that.
      
      Depending on the used SSD, we have seen up to 1.8 Watt lower system
      idle power usage and up to 30°C lower SSD controller temperatures in
      our tests, when we set med_power_with_dipm manually. I have provided a
      table showing seven different SATA SSDs from ATP, Intel/Solidigm and
      Samsung [2].
      
      Intel lists a total of 3 SATA controller IDs (4B60, 4B62, 4B63) in [1]
      for those mobile PCHs.
      This commit just adds 0x4b63 as I do not have test systems with 0x4b60
      and 0x4b62 SATA controllers.
      I have tested this patch with a system which uses 0x4b63 as SATA
      controller.
      
      [1] https://sata-io.org/product/8803
      [2] https://www.thomas-krenn.com/en/wiki/SATA_Link_Power_Management#Example_LES_v4
      
      Signed-off-by: default avatarWerner Fischer <devlists@wefi.net>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarDamien Le Moal <dlemoal@kernel.org>
      2a2df98e
  2. Aug 28, 2023
    • Michael Schmitz's avatar
      ata: pata_falcon: add data_swab option to byte-swap disk data · 8847d42d
      Michael Schmitz authored
      
      
      Some users of pata_falcon on Q40 have IDE disks in default
      IDE little endian byte order, whereas legacy disks use
      host-native big-endian byte order as on the Atari Falcon.
      
      Add module parameter 'data_swab' to allow connecting drives
      with non-native data byte order. Drives selected by the
      data_swap bit mask will have their user data byte-swapped to
      host byte order, i.e. 'pata_falcon.data_swab=2' will byte-swap
      all user data on drive B, leaving data on drive A in native
      byte order. On Q40, drives on a second IDE interface may be
      added to the bit mask as bits 2 and 3.
      
      Default setting is no byte swapping, i.e. compatibility with
      the native Falcon or Q40 operating system disk format.
      
      Cc: William R Sowerbutts <will@sowerbutts.com>
      Cc: Finn Thain <fthain@linux-m68k.org>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Tested-by: default avatarWilliam R Sowerbutts <will@sowerbutts.com>
      Signed-off-by: default avatarMichael Schmitz <schmitzmic@gmail.com>
      Reviewed-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Reviewed-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
      Signed-off-by: default avatarDamien Le Moal <dlemoal@kernel.org>
      8847d42d
    • Michael Schmitz's avatar
      ata: pata_falcon: fix IO base selection for Q40 · 8a1f00b7
      Michael Schmitz authored
      With commit 44b1fbc0
      
       ("m68k/q40: Replace q40ide driver
      with pata_falcon and falconide"), the Q40 IDE driver was
      replaced by pata_falcon.c.
      
      Both IO and memory resources were defined for the Q40 IDE
      platform device, but definition of the IDE register addresses
      was modeled after the Falcon case, both in use of the memory
      resources and in including register shift and byte vs. word
      offset in the address.
      
      This was correct for the Falcon case, which does not apply
      any address translation to the register addresses. In the
      Q40 case, all of device base address, byte access offset
      and register shift is included in the platform specific
      ISA access translation (in asm/mm_io.h).
      
      As a consequence, such address translation gets applied
      twice, and register addresses are mangled.
      
      Use the device base address from the platform IO resource
      for Q40 (the IO address translation will then add the correct
      ISA window base address and byte access offset), with register
      shift 1. Use MMIO base address and register shift 2 as before
      for Falcon.
      
      Encode PIO_OFFSET into IO port addresses for all registers
      for Q40 except the data transfer register. Encode the MMIO
      offset there (pata_falcon_data_xfer() directly uses raw IO
      with no address translation).
      
      Reported-by: default avatarWilliam R Sowerbutts <will@sowerbutts.com>
      Closes: https://lore.kernel.org/r/CAMuHMdUU62jjunJh9cqSqHT87B0H0A4udOOPs=WN7WZKpcagVA@mail.gmail.com
      Link: https://lore.kernel.org/r/CAMuHMdUU62jjunJh9cqSqHT87B0H0A4udOOPs=WN7WZKpcagVA@mail.gmail.com
      Fixes: 44b1fbc0
      
       ("m68k/q40: Replace q40ide driver with pata_falcon and falconide")
      Cc: stable@vger.kernel.org
      Cc: Finn Thain <fthain@linux-m68k.org>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Tested-by: default avatarWilliam R Sowerbutts <will@sowerbutts.com>
      Signed-off-by: default avatarMichael Schmitz <schmitzmic@gmail.com>
      Reviewed-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Reviewed-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
      Signed-off-by: default avatarDamien Le Moal <dlemoal@kernel.org>
      8a1f00b7
  3. Aug 25, 2023
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