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  1. Aug 30, 2023
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  9. Aug 24, 2023
    • Nathan Chancellor's avatar
      ASoC: cs42l43: Initialize ret in default case in cs42l43_pll_ev() · a7404843
      Nathan Chancellor authored 
      clang warns (or errors with CONFIG_WERROR=y):

  sound/soc/codecs/cs42l43.c:1371:2: error: variable 'ret' is used uninitialized whenever switch default is taken [-Werror,-Wsometimes-uninitialized]
   1371 |         default:
        |         ^~~~~~~
  sound/soc/codecs/cs42l43.c:1377:9: note: uninitialized use occurs here
   1377 |         return ret;
        |                ^~~
  sound/soc/codecs/cs42l43.c:1349:9: note: initialize the variable 'ret' to silence this warning
   1349 |         int ret;
        |                ^
        |                 = 0
  1 error generated.

Initialize ret to 0 in the default case, as there was nothing to do for
other event types.

Closes: https://github.com/ClangBuiltLinux/linux/issues/1922
Fixes: fc918cbe

 ("ASoC: cs42l43: Add support for the cs42l43")
Signed-off-by: default avatarNathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20230823-cs42l43_pll_ev-init-ret-v1-1-5836f1ad5dad@kernel.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      a7404843
    • Mark Brown's avatar
      Add I2S support for the StarFive JH7110 SoC · 1a512d13
      Mark Brown authored 
      Merge series from Xingyu Wu <xingyu.wu@starfivetech.com>:

This patch series adds I2S support for the StarFive JH7110 RISC-V
SoC based on Designware I2S controller. There has three I2S channels
(RX/TX0/TX1) on the JH7110 SoC, one of which is for record(RX) and
two for playback(TX).

The first patch adds support for the StarFive JH7110 SoC in the
Designware I2S bindings.
The second patch adds the ops to get data from platform bus in the
I2S driver.
The third patch adds support for the StarFive JH7110 SoC in
the Designware I2S driver.
The fourth patch fixes the name of I2STX1 pinmux.
The last patch adds device node of I2S RX/TX0/TX1 in JH7110 dts.

This patch series is based on Linux-next(20230818) which is merge
clock, syscon and dma nodes for the StarFive JH7110 SoC.

The series has been tested and works normally on the VisionFive 2
board by plugging an audio expansion board.
      1a512d13
    • Mark Brown's avatar
      ASoC: rsnd: tidyup ADG · fd53c16b
      Mark Brown authored 
      Merge series from Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>:

Renesas Sound has ADG for clock control. Basically it needs
accurately divisible external input clock. But sometimes
sometimes it doesn't have to be accurate for some reason.

We can use ADG clk_i for such case. It came from CPG as
very high rate clock, but is not accurately divisible for
48kHz/44.1kHz rate, but enough for approximate rate.

This patch set support such use case.
      fd53c16b
    • Kuninori Morimoto's avatar
      ASoC: audio-graph-card2: add comment for format property · ea2cb26a
      Kuninori Morimoto authored 
      

We don't need to have "format" property on DT any more if
CPU/Codec driver has .auto_selectable_formats settings
on snd_soc_dai_ops. The sample dtsi doesn't have it.
To avoid user confusion, this patch indicates it on comment.

Signed-off-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87edjuzk2p.wl-kuninori.morimoto.gx@renesas.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      ea2cb26a
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