x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN

commit a331f5fd

 upstream.

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com


Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>