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Commit a331f5fd authored by Tony Luck's avatar Tony Luck Committed by Ingo Molnar
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x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN 



New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
parent 301cddc2
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