PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

commit b3ddd8efc4aa70bee02da0b5ecc2ef5099916a71 from
https://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v5.15

The Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has a few changes from the existing CPM block:

  - CPM5 has dedicated register space for control and status registers.

  - CPM5 legacy interrupt handling needs additional register bit to enable
    and handle legacy interrupts.

Add support for the new CPM5 features.

[bhelgaas: compare variant->version with CPM5 explicitly]
Link: https://lore.kernel.org/r/20220705105646.16980-3-bharat.kumar.gogada@xilinx.com


Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
State: upstream (51f1ffc0)
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>