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Commit 1d9d8fe1 authored by Bharat Kumar Gogada's avatar Bharat Kumar Gogada Committed by Quanyang Wang
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dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port

commit e776db670bf00e45443ca49295aac26573c498be from
https://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v5.15

Xilinx Versal Premium series has CPM5 block which supports Root Port
functionality at Gen5 speed.

Add support for YAML schemas documentation for Versal CPM5 Root Port driver.

Link: https://lore.kernel.org/r/20220705105646.16980-2-bharat.kumar.gogada@xilinx.com


Signed-off-by: default avatarBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
State: upstream (49f40703)
Signed-off-by: default avatarQuanyang Wang <quanyang.wang@windriver.com>
parent cba8b06d
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