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Commit 25c570c7 authored by Meng Li's avatar Meng Li Committed by Liwei Song
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usb: dwc2: add new compatible for Intel SoCFPGA Stratix10 platform

Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
the Stratix platform also does not support clock-gating. The commit
3d8d3504

("usb: dwc2: Add platform specific data for Intel's Agilex")
had fixed this issue. So, add the essential compatible to also use the
specific data on Stratix10 platform.

Signed-off-by: default avatarMeng Li <Meng.Li@windriver.com>
Signed-off-by: default avatarBruce Ashfield <bruce.ashfield@gmail.com>
Signed-off-by: default avatarLiwei Song <liwei.song@windriver.com>
parent 1b856601
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