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Commit 98450d02 authored by Simon Glass's avatar Simon Glass Committed by Albert ARIBAUD
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tegra: mmc: Support operation with dcache enabled



When the data cache is enabled we must flush on write and invalidate
on read. We also check that buffers are aligned to data cache lines
boundaries. With recent work in U-Boot this should generally be the case
but the warnings will catch problems.

Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
parent ca28090d
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