Commit f9efefdb authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' into clk-next 

 - Convert Baikal-T1 CCU driver to platform driver
 - Split reset support out of primary Baikal-T1 CCU driver
 - Add some missing clks required for RPiVid Video Decoder on RaspberryPi
 - Mark PLLC critical on bcm2835
 - Support for Renesas VersaClock7 clock generator family

* clk-baikal:
  clk: baikal-t1: Convert to platform device driver
  clk: baikal-t1: Add DDR/PCIe directly controlled resets support
  dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs
  clk: baikal-t1: Move reset-controls code into a dedicated module
  clk: baikal-t1: Add SATA internal ref clock buffer
  clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent
  clk: baikal-t1: Fix invalid xGMAC PTP clock divider
  clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD

* clk-broadcom:
  clk: bcm: rpi: Add support for VEC clock
  clk: bcm: rpi: Handle pixel clock in firmware
  clk: bcm: rpi: Add support HEVC clock
  clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration
  clk: bcm2835: Round UART input clock up
  clk: bcm2835: Make peripheral PLLC critical

* clk-vc5:
  clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
  dt-bindings: clock: vc5: Add 5P49V6975
  clk: vc5: Use regmap_{set,clear}_bits() where appropriate
  clk: vc5: Check IO access results

* clk-versaclock:
  clk: Renesas versaclock7 ccf device driver
  dt-bindings: Renesas versaclock7 device tree bindings
parents b7f257ce c4e05443 1777cb60 d8473831 48c5e98f

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

+2 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ properties: 
      - idt,5p49v5935

      - idt,5p49v6901

      - idt,5p49v6965

      - idt,5p49v6975



  reg:

    description: I2C device address
@@ -134,6 +135,7 @@ allOf: 
          enum:

            - idt,5p49v5933

            - idt,5p49v5935

            - idt,5p49v6975

    then:

      # Devices with builtin crystal + optional external input

      properties:

Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml

0 → 100644
+64 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas Versaclock7 Programmable Clock Device Tree Bindings



maintainers:

  - Alex Helms <alexander.helms.jy@renesas.com>



description: |

  Renesas Versaclock7 is a family of configurable clock generator and

  jitter attenuator ICs with fractional and integer dividers.



properties:

  '#clock-cells':

    const: 1



  compatible:

    enum:

      - renesas,rc21008a



  reg:

    maxItems: 1



  clocks:

    items:

      - description: External crystal or oscillator



  clock-names:

    items:

      - const: xin



required:

  - '#clock-cells'

  - compatible

  - reg

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    vc7_xin: clock {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <49152000>;

    };



    i2c@0 {

        reg = <0x0 0x100>;

        #address-cells = <1>;

        #size-cells = <0>;



        vc7: clock-controller@9 {

            compatible = "renesas,rc21008a";

            reg = <0x9>;

            #clock-cells = <1>;

            clocks = <&vc7_xin>;

            clock-names = "xin";

        };

    };

MAINTAINERS

+6 −0
Original line number Diff line number Diff line
@@ -17442,6 +17442,12 @@ S: Maintained 
F:	Documentation/devicetree/bindings/mtd/renesas-nandc.yaml

F:	drivers/mtd/nand/raw/renesas-nand-controller.c









RENESAS VERSACLOCK 7 CLOCK DRIVER









M:	Alex Helms <alexander.helms.jy@renesas.com>









S:	Maintained









F:	Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml









F:	drivers/clk/clk-versaclock7.c

















RESET CONTROLLER FRAMEWORK









M:	Philipp Zabel <p.zabel@pengutronix.de>









S:	Maintained

























drivers/clk/Kconfig



+9
−0






























Original line number
Diff line number
Diff line







@@ -377,6 +377,15 @@ config COMMON_CLK_VC5







	  This driver supports the IDT VersaClock 5 and VersaClock 6









	  programmable clock generators.



















config COMMON_CLK_VC7









	tristate "Clock driver for Renesas Versaclock 7 devices"









	depends on I2C









	depends on OF









	select REGMAP_I2C









	help









	  Renesas Versaclock7 is a family of configurable clock generator









	  and jitter attenuator ICs with fractional and integer dividers.



















config COMMON_CLK_STM32MP135









	def_bool COMMON_CLK && MACH_STM32MP13









	help
































drivers/clk/Makefile



+1
−0






























Original line number
Diff line number
Diff line







@@ -73,6 +73,7 @@ obj-$(CONFIG_CLK_TWL6040)		+= clk-twl6040.o







obj-$(CONFIG_ARCH_VT8500)		+= clk-vt8500.o









obj-$(CONFIG_COMMON_CLK_RS9_PCIE)	+= clk-renesas-pcie.o









obj-$(CONFIG_COMMON_CLK_VC5)		+= clk-versaclock5.o









obj-$(CONFIG_COMMON_CLK_VC7)		+= clk-versaclock7.o









obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o









obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o