Commit b7f257ce authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-fixed-rate', 'clk-spreadtrum', 'clk-pxa' and 'clk-ti' into clk-next 

 - More devm helpers for fixed rate registration
 - Add Spreadtrum UMS512 SoC clk support
 - Various PXA168 clk driver fixes

* clk-fixed-rate:
  clk: fixed-rate: add devm_clk_hw_register_fixed_rate
  clk: asm9260: use parent index to link the reference clock

* clk-spreadtrum:
  clk: sprd: Add clocks support for UMS512

* clk-pxa:
  clk: pxa: add a check for the return value of kzalloc()
  clk: mmp: pxa168: control shared SDH bits with separate clock
  dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks
  clk: mmp: pxa168: add clocks for SDH2 and SDH3
  dt-bindings: marvell,pxa168: add clock id for SDH3
  clk: mmp: pxa168: fix GPIO clock enable bits
  clk: mmp: pxa168: add muxes for more peripherals
  clk: mmp: pxa168: fix incorrect parent clocks
  clk: mmp: pxa168: fix const-correctness
  clk: mmp: pxa168: add new clocks for peripherals
  dt-bindings: marvell,pxa168: add clock ids for additional dividers
  clk: mmp: pxa168: fix incorrect dividers
  clk: mmp: pxa168: add additional register defines

* clk-ti:
  clk: davinci: cfgchip: Use dev_err_probe() helper
  clk: davinci: pll: fix spelling typo in comment
  MAINTAINERS: add header file to TI DAVINCI SERIES CLOCK DRIVER
parents 26bebbfe 1d7d2065 af3bd365 117a1542 3475c885

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -20308,6 +20308,7 @@ R: Sekhar Nori <nsekhar@ti.com> 
S:	Maintained

F:	Documentation/devicetree/bindings/clock/ti/davinci/

F:	drivers/clk/davinci/

F:	include/linux/clk/davinci.h









TI DAVINCI SERIES GPIO DRIVER









M:	Keerthy <j-keerthy@ti.com>

























drivers/clk/clk-asm9260.c



+12
−17






























Original line number
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Diff line







@@ -80,7 +80,7 @@ struct asm9260_mux_clock {







	u8			mask;









	u32			*table;









	const char		*name;









	const char		**parent_names;









	const struct clk_parent_data *parent_data;









	u8			num_parents;









	unsigned long		offset;









	unsigned long		flags;








@@ -232,10 +232,10 @@ static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {







		HW_AHBCLKCTRL1,	16 },









};



















static const char __initdata *main_mux_p[] =   { NULL, NULL };









static const char __initdata *i2s0_mux_p[] =   { NULL, NULL, "i2s0m_div"};









static const char __initdata *i2s1_mux_p[] =   { NULL, NULL, "i2s1m_div"};









static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"};









static struct clk_parent_data __initdata main_mux_p[] =   { { .index = 0, }, { .name = "pll" } };









static struct clk_parent_data __initdata i2s0_mux_p[] =   { { .index = 0, }, { .name = "pll" }, { .name = "i2s0m_div"} };









static struct clk_parent_data __initdata i2s1_mux_p[] =   { { .index = 0, }, { .name = "pll" }, { .name = "i2s1m_div"} };









static struct clk_parent_data __initdata clkout_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "rtc"} };









static u32 three_mux_table[] = {0, 1, 3};



















static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {








@@ -255,9 +255,10 @@ static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {

















static void __init asm9260_acc_init(struct device_node *np)









{









	struct clk_hw *hw;









	struct clk_hw *hw, *pll_hw;









	struct clk_hw **hws;









	const char *ref_clk, *pll_clk = "pll";









	const char *pll_clk = "pll";









	struct clk_parent_data pll_parent_data = { .index = 0 };









	u32 rate;









	int n;


















@@ -274,21 +275,15 @@ static void __init asm9260_acc_init(struct device_node *np)







	/* register pll */









	rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;



















	/* TODO: Convert to DT parent scheme */









	ref_clk = of_clk_get_parent_name(np, 0);









	hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk,









			ref_clk, NULL, NULL, 0, rate, 0,









			CLK_FIXED_RATE_PARENT_ACCURACY);



















	if (IS_ERR(hw))









	pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data,









							0, rate);









	if (IS_ERR(pll_hw))









		panic("%pOFn: can't register REFCLK. Check DT!", np);



















	for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {









		const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];



















		mc->parent_names[0] = ref_clk;









		mc->parent_names[1] = pll_clk;









		hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,









		hw = clk_hw_register_mux_table_parent_data(NULL, mc->name, mc->parent_data,









				mc->num_parents, mc->flags, base + mc->offset,









				0, mc->mask, 0, mc->table, &asm9260_clk_lock);









	}
































drivers/clk/clk-fixed-rate.c



+24
−4






























Original line number
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Diff line







@@ -49,12 +49,24 @@ const struct clk_ops clk_fixed_rate_ops = {







};









EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);



















static void devm_clk_hw_register_fixed_rate_release(struct device *dev, void *res)









{









	struct clk_fixed_rate *fix = res;



















	/*









	 * We can not use clk_hw_unregister_fixed_rate, since it will kfree()









	 * the hw, resulting in double free. Just unregister the hw and let









	 * devres code kfree() it.









	 */









	clk_hw_unregister(&fix->hw);









}



















struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,









		struct device_node *np, const char *name,









		const char *parent_name, const struct clk_hw *parent_hw,









		const struct clk_parent_data *parent_data, unsigned long flags,









		unsigned long fixed_rate, unsigned long fixed_accuracy,









		unsigned long clk_fixed_flags)









		unsigned long clk_fixed_flags, bool devm)









{









	struct clk_fixed_rate *fixed;









	struct clk_hw *hw;








@@ -62,6 +74,10 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,







	int ret = -EINVAL;



















	/* allocate fixed-rate clock */









	if (devm)









		fixed = devres_alloc(devm_clk_hw_register_fixed_rate_release,









				     sizeof(*fixed), GFP_KERNEL);









	else









		fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);









	if (!fixed)









		return ERR_PTR(-ENOMEM);








@@ -90,9 +106,13 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,







	else









		ret = of_clk_hw_register(np, hw);









	if (ret) {









		if (devm)









			devres_free(fixed);









		else









			kfree(fixed);









		hw = ERR_PTR(ret);









	}









	} else if (devm)









		devres_add(dev, fixed);



















	return hw;









}
































drivers/clk/davinci/da8xx-cfgchip.c



+1
−2






























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@@ -510,8 +510,7 @@ da8xx_cfgchip_register_usb0_clk48(struct device *dev,

















	fck_clk = devm_clk_get(dev, "fck");









	if (IS_ERR(fck_clk)) {









		if (PTR_ERR(fck_clk) != -EPROBE_DEFER)









			dev_err(dev, "Missing fck clock\n");









		dev_err_probe(dev, PTR_ERR(fck_clk), "Missing fck clock\n");









		return ERR_CAST(fck_clk);









	}










































drivers/clk/davinci/pll.c



+1
−1






























Original line number
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Diff line







@@ -98,7 +98,7 @@







 * @hw: clk_hw for the pll









 * @base: Base memory address









 * @pllm_min: The minimum allowable PLLM[PLLM] value









 * @pllm_max: The maxiumum allowable PLLM[PLLM] value









 * @pllm_max: The maximum allowable PLLM[PLLM] value









 * @pllm_mask: Bitmask for PLLM[PLLM] value









 */









struct davinci_pll_clk {