Commit 26bebbfe authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner'... 

Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner' and 'clk-imx' into clk-next

* clk-rockchip:
  dt-bindings: clock: rockchip: change SPDX-License-Identifier
  dt-bindings: clock: convert rockchip,rk3128-cru.txt to YAML
  clk: rockchip: Add clock controller support for RV1126 SoC
  dt-bindings: clock: rockchip: Document RV1126 CRU
  clk: rockchip: Add dt-binding header for RV1126
  clk: rockchip: Add MUXTBL variant

* clk-renesas:
  clk: renesas: r8a779g0: Add EtherAVB clocks
  clk: renesas: r8a779g0: Add PFC/GPIO clocks
  clk: renesas: r8a779g0: Add I2C clocks
  clk: renesas: r8a779g0: Add watchdog clock
  dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC
  clk: renesas: r8a779f0: Add MSIOF clocks
  clk: renesas: r9a09g011: Add IIC clock and reset entries
  clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info
  clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks
  clk: renesas: r8a779f0: Add CMT clocks
  clk: renesas: r8a779f0: Add SDH0 clock

* clk-microchip:
  clk: at91: sama5d2: Add Generic Clocks for UART/USART
  clk: microchip: add PolarFire SoC fabric clock support
  dt-bindings: clk: add PolarFire SoC fabric clock ids
  dt-bindings: clk: document PolarFire SoC fabric clocks
  dt-bindings: clk: rename mpfs-clkcfg binding
  clk: microchip: mpfs: update module authorship & licencing
  clk: microchip: mpfs: convert periph_clk to clk_gate
  clk: microchip: mpfs: convert cfg_clk to clk_divider
  clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()
  clk: microchip: mpfs: simplify control reg access
  clk: microchip: mpfs: move id & offset out of clock structs
  clk: microchip: mpfs: add MSS pll's set & round rate
  MAINTAINERS: add polarfire soc reset controller
  reset: add polarfire soc reset support
  clk: microchip: mpfs: add reset controller
  dt-bindings: clk: microchip: mpfs: add reset controller support
  clk: microchip: mpfs: make the rtc's ahb clock critical
  clk: microchip: mpfs: fix clk_cfg array bounds violation

* clk-allwinner:
  clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helper
  clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helper
  clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helper
  clk: sunxi-ng: d1: Limit PLL rates to stable ranges

* clk-imx:
  clk: imx: scu: fix memleak on platform_device_add() fails
  clk: imx93: add SAI IPG clk
  clk: imx93: add MU1/2 clock
  clk: imx93: switch to use new clk gate API
  clk: imx: add i.MX93 clk gate
  clk: imx: clk-composite-93: check white_list
  clk: imx: clk-composite-93: check slice busy
  dt-bindings: clock: imx93-clock: add more MU/SAI clocks
  dt-bindings: clock: imx8mm: don't use multiple blank lines
  clk: imx8mp: tune the order of enet_qos_root_clk
parents a64b79c0 9e1343ed acb84a16 50cf94b4 d772c937 855ae87a

Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry



maintainers:

  - Conor Dooley <conor.dooley@microchip.com>



description: |

  Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of

  these blocks contains two PLLs and 2 DLLs & are located in the four corners of

  the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:

  https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html



properties:

  compatible:

    const: microchip,mpfs-ccc



  reg:

    items:

      - description: PLL0's control registers

      - description: PLL1's control registers

      - description: DLL0's control registers

      - description: DLL1's control registers



  clocks:

    description:

      The CCC PLL's have two input clocks. It is required that even if the input

      clocks are identical that both are provided.

    minItems: 2

    items:

      - description: PLL0's refclk0

      - description: PLL0's refclk1

      - description: PLL1's refclk0

      - description: PLL1's refclk1

      - description: DLL0's refclk

      - description: DLL1's refclk



  clock-names:

    minItems: 2

    items:

      - const: pll0_ref0

      - const: pll0_ref1

      - const: pll1_ref0

      - const: pll1_ref1

      - const: dll0_ref

      - const: dll1_ref



  '#clock-cells':

    const: 1

    description: |

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell.

      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of

      PolarFire clock IDs.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@38100000 {

        compatible = "microchip,mpfs-ccc";

        reg = <0x38010000 0x1000>, <0x38020000 0x1000>,

              <0x39010000 0x1000>, <0x39020000 0x1000>;

        #clock-cells = <1>;

        clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,

                  <&refclk_ccc>, <&refclk_ccc>;

        clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",

                      "dll0_ref", "dll1_ref";

    };

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml→Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

+16 −3
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#

$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip PolarFire Clock Control Module Binding
@@ -40,8 +40,21 @@ properties: 
    const: 1

    description: |

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h

      for the full list of PolarFire clock IDs.

      ID in its "clocks" phandle cell.

      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of

      PolarFire clock IDs.



  resets:

    maxItems: 1



  '#reset-cells':

    description:

      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from

      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired

      peripheral via the clock ID in its "resets" phandle cell.

      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of

      PolarFire clock IDs.

    const: 1



required:

  - compatible

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

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@@ -24,7 +24,7 @@ description: | 
properties:

  compatible:

    enum:

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a09g011-cpg # RZ/V2M

Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml

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# SPDX-License-Identifier: GPL-2.0

# SPDX-License-Identifier: (GPL-2.0+ OR MIT)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#

Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml

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# SPDX-License-Identifier: GPL-2.0

# SPDX-License-Identifier: (GPL-2.0+ OR MIT)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#