Commit 50cf94b4 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-microchip-6.1' of... 

Merge tag 'clk-microchip-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip

Pull Microchip clk driver updates from Claudiu Beznea:

Microchip AT91:
- add generic clocks for U(S)ART available on SAMA5D2 SoCs

Microchip Polarfire:
- reset controller support for Polarfire clocks
- .round_rate and .set rate support for clk-mpfs
- code cleanup for clk-mpfs
- PLL support for PolarFire SoC's Clock Conditioning Circuitry

* tag 'clk-microchip-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  clk: at91: sama5d2: Add Generic Clocks for UART/USART
  clk: microchip: add PolarFire SoC fabric clock support
  dt-bindings: clk: add PolarFire SoC fabric clock ids
  dt-bindings: clk: document PolarFire SoC fabric clocks
  dt-bindings: clk: rename mpfs-clkcfg binding
  clk: microchip: mpfs: update module authorship & licencing
  clk: microchip: mpfs: convert periph_clk to clk_gate
  clk: microchip: mpfs: convert cfg_clk to clk_divider
  clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()
  clk: microchip: mpfs: simplify control reg access
  clk: microchip: mpfs: move id & offset out of clock structs
  clk: microchip: mpfs: add MSS pll's set & round rate
  MAINTAINERS: add polarfire soc reset controller
  reset: add polarfire soc reset support
  clk: microchip: mpfs: add reset controller
  dt-bindings: clk: microchip: mpfs: add reset controller support
  clk: microchip: mpfs: make the rtc's ahb clock critical
  clk: microchip: mpfs: fix clk_cfg array bounds violation
parents 568035b0 935edf0c

Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml

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+80 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry



maintainers:

  - Conor Dooley <conor.dooley@microchip.com>



description: |

  Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of

  these blocks contains two PLLs and 2 DLLs & are located in the four corners of

  the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:

  https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html



properties:

  compatible:

    const: microchip,mpfs-ccc



  reg:

    items:

      - description: PLL0's control registers

      - description: PLL1's control registers

      - description: DLL0's control registers

      - description: DLL1's control registers



  clocks:

    description:

      The CCC PLL's have two input clocks. It is required that even if the input

      clocks are identical that both are provided.

    minItems: 2

    items:

      - description: PLL0's refclk0

      - description: PLL0's refclk1

      - description: PLL1's refclk0

      - description: PLL1's refclk1

      - description: DLL0's refclk

      - description: DLL1's refclk



  clock-names:

    minItems: 2

    items:

      - const: pll0_ref0

      - const: pll0_ref1

      - const: pll1_ref0

      - const: pll1_ref1

      - const: dll0_ref

      - const: dll1_ref



  '#clock-cells':

    const: 1

    description: |

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell.

      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of

      PolarFire clock IDs.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@38100000 {

        compatible = "microchip,mpfs-ccc";

        reg = <0x38010000 0x1000>, <0x38020000 0x1000>,

              <0x39010000 0x1000>, <0x39020000 0x1000>;

        #clock-cells = <1>;

        clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,

                  <&refclk_ccc>, <&refclk_ccc>;

        clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",

                      "dll0_ref", "dll1_ref";

    };

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml→Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

+16 −3
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#

$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip PolarFire Clock Control Module Binding
@@ -40,8 +40,21 @@ properties: 
    const: 1

    description: |

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h

      for the full list of PolarFire clock IDs.

      ID in its "clocks" phandle cell.

      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of

      PolarFire clock IDs.



  resets:

    maxItems: 1



  '#reset-cells':

    description:

      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from

      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired

      peripheral via the clock ID in its "resets" phandle cell.

      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of

      PolarFire clock IDs.

    const: 1



required:

  - compatible

MAINTAINERS

+1 −0
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@@ -17532,6 +17532,7 @@ F: drivers/char/hw_random/mpfs-rng.c 
F:	drivers/clk/microchip/clk-mpfs.c

F:	drivers/mailbox/mailbox-mpfs.c

F:	drivers/pci/controller/pcie-microchip-host.c

F:	drivers/reset/reset-mpfs.c

F:	drivers/rtc/rtc-mpfs.c

F:	drivers/soc/microchip/

F:	drivers/spi/spi-microchip-core.c

drivers/clk/at91/sama5d2.c

+10 −0
Original line number Diff line number Diff line
@@ -120,6 +120,16 @@ static const struct { 
	struct clk_range r;

	int chg_pid;

} sama5d2_gck[] = {

	{ .n = "flx0_gclk",   .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "flx1_gclk",   .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "flx2_gclk",   .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "flx3_gclk",   .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "flx4_gclk",   .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "uart0_gclk",  .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "uart1_gclk",  .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "uart2_gclk",  .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "uart3_gclk",  .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "uart4_gclk",  .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },

	{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },

	{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },

	{ .n = "tcb0_gclk",   .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },

drivers/clk/microchip/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -6,5 +6,6 @@ config COMMON_CLK_PIC32 
config MCHP_CLK_MPFS

	bool "Clk driver for PolarFire SoC"

	depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST

	select AUXILIARY_BUS

	help

	  Supports Clock Configuration for PolarFire SoC