Commit 48c5e98f authored by Alex Helms's avatar Alex Helms Committed by Stephen Boyd
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clk: Renesas versaclock7 ccf device driver



Renesas Versaclock7 is a family of configurable clock generator ICs
with fractional and integer dividers. This driver has basic support
for the RC21008A device, a clock synthesizer with a crystal input and
8 outputs. The supports changing the FOD and IOD rates, and each
output can be gated.

Signed-off-by: default avatarAlex Helms <alexander.helms.jy@renesas.com>
Link: https://lore.kernel.org/r/20220912183613.22213-3-alexander.helms.jy@renesas.com


Tested-by: default avatarSaeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 09d18556
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Original line number Original line Diff line number Diff line
@@ -17445,6 +17445,7 @@ RENESAS VERSACLOCK 7 CLOCK DRIVER
M:	Alex Helms <alexander.helms.jy@renesas.com>
M:	Alex Helms <alexander.helms.jy@renesas.com>
S:	Maintained
S:	Maintained
F:	Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
F:	Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
F:	drivers/clk/clk-versaclock7.c
RESET CONTROLLER FRAMEWORK
RESET CONTROLLER FRAMEWORK
M:	Philipp Zabel <p.zabel@pengutronix.de>
M:	Philipp Zabel <p.zabel@pengutronix.de>
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@@ -377,6 +377,15 @@ config COMMON_CLK_VC5
	  This driver supports the IDT VersaClock 5 and VersaClock 6
	  This driver supports the IDT VersaClock 5 and VersaClock 6
	  programmable clock generators.
	  programmable clock generators.


config COMMON_CLK_VC7
	tristate "Clock driver for Renesas Versaclock 7 devices"
	depends on I2C
	depends on OF
	select REGMAP_I2C
	help
	  Renesas Versaclock7 is a family of configurable clock generator
	  and jitter attenuator ICs with fractional and integer dividers.

config COMMON_CLK_STM32MP135
config COMMON_CLK_STM32MP135
	def_bool COMMON_CLK && MACH_STM32MP13
	def_bool COMMON_CLK && MACH_STM32MP13
	help
	help
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@@ -73,6 +73,7 @@ obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_ARCH_VT8500)		+= clk-vt8500.o
obj-$(CONFIG_ARCH_VT8500)		+= clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_RS9_PCIE)	+= clk-renesas-pcie.o
obj-$(CONFIG_COMMON_CLK_RS9_PCIE)	+= clk-renesas-pcie.o
obj-$(CONFIG_COMMON_CLK_VC5)		+= clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_VC5)		+= clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_VC7)		+= clk-versaclock7.o
obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o
obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o


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