Commit f691c9b5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-nvidia', 'clk-imx', 'clk-samsung' and 'clk-qcom' into clk-next 

* clk-nvidia:
  clk: tegra: Support runtime PM and power domain
  clk: tegra: Make vde a child of pll_p on tegra114

* clk-imx:
  clk: imx8mp: Fix the parent clk of the audio_root_clk
  clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h
  clk: imx8mn: Fix imx8mn_clko1_sels
  clk: imx: Use div64_ul instead of do_div
  clk: imx: imx8ulp: set suppress_bind_attrs to true

* clk-samsung:
  clk: samsung: Add initial Exynos7885 clock driver
  clk: samsung: clk-pll: Add support for pll1417x
  clk: samsung: Make exynos850_register_cmu shared
  dt-bindings: clock: Document Exynos7885 CMU bindings
  dt-bindings: clock: Add bindings definitions for Exynos7885 CMU
  clk: samsung: exynos850: Add missing sysreg clocks
  dt-bindings: clock: Add bindings for Exynos850 sysreg clocks
  clk: samsung: exynos850: Register clocks early
  clk: samsung: exynos850: Keep some crucial clocks running
  clk: samsung: exynos850: Implement CMU_CMGP domain
  dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP
  clk: samsung: exynos850: Implement CMU_APM domain
  dt-bindings: clock: Add bindings for Exynos850 CMU_APM
  clk: samsung: Update CPU clk registration
  clk: samsung: Remove meaningless __init and extern from header files
  clk: samsung: remove __clk_lookup() usage
  dt-bindings: clock: samsung: add IDs for some core clocks

* clk-qcom: (25 commits)
  clk: qcom: gcc-sc7280: Mark gcc_cfg_noc_lpass_clk always enabled
  clk: qcom: clk-alpha-pll: Increase PLL lock detect poll time
  clk: qcom: turingcc-qcs404: explicitly include clk-provider.h
  clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h
  clk: qcom: mmcc-apq8084: explicitly include clk-provider.h
  clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h
  clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h
  clk: qcom: gcc-sm6350: explicitly include clk-provider.h
  clk: qcom: gcc-msm8994: explicitly include clk-provider.h
  clk: qcom: gcc-sm8350: explicitly include clk-provider.h
  clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver
  dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller
  clk: qcom: Add clock driver for SM8450
  clk: qcom: Add SDX65 GCC support
  clk: qcom: Add LUCID_EVO PLL type for SDX65
  dt-bindings: clock: Add SM8450 GCC clock bindings
  dt-bindings: clock: Add SDX65 GCC clock bindings
  clk: qcom: rpmh: add support for SM8450 rpmh clocks
  dt-bindings: clock: Add RPMHCC bindings for SM8450
  clk: qcom: smd-rpm: Drop binary value handling for buffered clock
  ...
parents 151768f3 fcfc6ea4 176a3200 14350ed9 87e55700

Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for MSM8976



maintainers:

  - Stephen Boyd <sboyd@kernel.org>

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on MSM8976.



  See also:

  - dt-bindings/clock/qcom,gcc-msm8976.h



properties:

  compatible:

    enum:

      - qcom,gcc-msm8976

      - qcom,gcc-msm8976-v1.1



  clocks:

    items:

      - description: XO source

      - description: Always-on XO source

      - description: Pixel clock from DSI PHY0

      - description: Byte clock from DSI PHY0

      - description: Pixel clock from DSI PHY1

      - description: Byte clock from DSI PHY1



  clock-names:

    items:

      - const: xo

      - const: xo_a

      - const: dsi0pll

      - const: dsi0pllbyte

      - const: dsi1pll

      - const: dsi1pllbyte



  vdd_gfx-supply:

    description:

      Phandle to voltage regulator providing power to the GX domain.



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - vdd_gfx-supply

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    clock-controller@1800000 {

      compatible = "qcom,gcc-msm8976";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

      reg = <0x1800000 0x80000>;



      clocks = <&xo_board>,

               <&xo_board>,

               <&dsi0_phy 1>,

               <&dsi0_phy 0>,

               <&dsi1_phy 1>,

               <&dsi1_phy 0>;



      clock-names = "xo",

                    "xo_a",

                    "dsi0pll",

                    "dsi0pllbyte",

                    "dsi1pll",

                    "dsi1pllbyte";



      vdd_gfx-supply = <&pm8004_s5>;

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for SDX65



maintainers:

  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SDX65



  See also:

  - dt-bindings/clock/qcom,gcc-sdx65.h



properties:

  compatible:

    const: qcom,gcc-sdx65



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source

      - description: PCIE Pipe clock source

      - description: USB3 phy wrapper pipe clock source

      - description: PLL test clock source (Optional clock)

    minItems: 5



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk

      - const: pcie_pipe_clk

      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk

      - const: core_bi_pll_test_se # Optional clock

    minItems: 5



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sdx65";

      reg = <0x100000 0x1f7400>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,

               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",

                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for SM8450



maintainers:

  - Vinod Koul <vkoul@kernel.org>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SM8450



  See also:

  - dt-bindings/clock/qcom,gcc-sm8450.h



properties:

  compatible:

    const: qcom,gcc-sm8450



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: PCIE 0 Pipe clock source (Optional clock)

      - description: PCIE 1 Pipe clock source (Optional clock)

      - description: PCIE 1 Phy Auxillary clock source (Optional clock)

      - description: UFS Phy Rx symbol 0 clock source (Optional clock)

      - description: UFS Phy Rx symbol 1 clock source (Optional clock)

      - description: UFS Phy Tx symbol 0 clock source (Optional clock)

      - description: USB3 Phy wrapper pipe clock source (Optional clock)

    minItems: 2



  clock-names:

    items:

      - const: bi_tcxo

      - const: sleep_clk

      - const: pcie_0_pipe_clk # Optional clock

      - const: pcie_1_pipe_clk # Optional clock

      - const: pcie_1_phy_aux_clk # Optional clock

      - const: ufs_phy_rx_symbol_0_clk # Optional clock

      - const: ufs_phy_rx_symbol_1_clk # Optional clock

      - const: ufs_phy_tx_symbol_0_clk # Optional clock

      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock

    minItems: 2



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sm8450";

      reg = <0x00100000 0x001f4200>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;

      clock-names = "bi_tcxo", "sleep_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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@@ -22,10 +22,12 @@ properties: 
      - qcom,sc8180x-rpmh-clk

      - qcom,sdm845-rpmh-clk

      - qcom,sdx55-rpmh-clk

      - qcom,sdx65-rpmh-clk

      - qcom,sm6350-rpmh-clk

      - qcom,sm8150-rpmh-clk

      - qcom,sm8250-rpmh-clk

      - qcom,sm8350-rpmh-clk

      - qcom,sm8450-rpmh-clk



  clocks:

    maxItems: 1

Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung Exynos7885 SoC clock controller



maintainers:

  - Dávid Virág <virag.david003@gmail.com>

  - Chanwoo Choi <cw00.choi@samsung.com>

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

  - Sylwester Nawrocki <s.nawrocki@samsung.com>

  - Tomasz Figa <tomasz.figa@gmail.com>



description: |

  Exynos7885 clock controller is comprised of several CMU units, generating

  clocks for different domains. Those CMU units are modeled as separate device

  tree nodes, and might depend on each other. The root clock in that root tree

  is an external clock: OSCCLK (26 MHz). This external clock must be defined

  as a fixed-rate clock in dts.



  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'dt-bindings/clock/exynos7885.h' header.



properties:

  compatible:

    enum:

      - samsung,exynos7885-cmu-top

      - samsung,exynos7885-cmu-core

      - samsung,exynos7885-cmu-peri



  clocks:

    minItems: 1

    maxItems: 10



  clock-names:

    minItems: 1

    maxItems: 10



  "#clock-cells":

    const: 1



  reg:

    maxItems: 1



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos7885-cmu-top



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)



        clock-names:

          items:

            - const: oscclk



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos7885-cmu-core



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_CORE bus clock (from CMU_TOP)

            - description: CCI clock (from CMU_TOP)

            - description: G3D clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_core_bus

            - const: dout_core_cci

            - const: dout_core_g3d



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos7885-cmu-peri



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_PERI bus clock (from CMU_TOP)

            - description: SPI0 clock (from CMU_TOP)

            - description: SPI1 clock (from CMU_TOP)

            - description: UART0 clock (from CMU_TOP)

            - description: UART1 clock (from CMU_TOP)

            - description: UART2 clock (from CMU_TOP)

            - description: USI0 clock (from CMU_TOP)

            - description: USI1 clock (from CMU_TOP)

            - description: USI2 clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_peri_bus

            - const: dout_peri_spi0

            - const: dout_peri_spi1

            - const: dout_peri_uart0

            - const: dout_peri_uart1

            - const: dout_peri_uart2

            - const: dout_peri_usi0

            - const: dout_peri_usi1

            - const: dout_peri_usi2



required:

  - compatible

  - "#clock-cells"

  - clocks

  - clock-names

  - reg



additionalProperties: false



examples:

  # Clock controller node for CMU_PERI

  - |

    #include <dt-bindings/clock/exynos7885.h>



    cmu_peri: clock-controller@10010000 {

        compatible = "samsung,exynos7885-cmu-peri";

        reg = <0x10010000 0x8000>;

        #clock-cells = <1>;



        clocks = <&oscclk>,

                 <&cmu_top CLK_DOUT_PERI_BUS>,

                 <&cmu_top CLK_DOUT_PERI_SPI0>,

                 <&cmu_top CLK_DOUT_PERI_SPI1>,

                 <&cmu_top CLK_DOUT_PERI_UART0>,

                 <&cmu_top CLK_DOUT_PERI_UART1>,

                 <&cmu_top CLK_DOUT_PERI_UART2>,

                 <&cmu_top CLK_DOUT_PERI_USI0>,

                 <&cmu_top CLK_DOUT_PERI_USI1>,

                 <&cmu_top CLK_DOUT_PERI_USI2>;

        clock-names = "oscclk",

                      "dout_peri_bus",

                      "dout_peri_spi0",

                      "dout_peri_spi1",

                      "dout_peri_uart0",

                      "dout_peri_uart1",

                      "dout_peri_uart2",

                      "dout_peri_usi0",

                      "dout_peri_usi1",

                      "dout_peri_usi2";

    };



...