Commit 87e55700 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-5.17' of... 

Merge tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull qcom clk driver updates from Bjorn Andersson:

This introduces bindings and drivers for the global clock controllers
found in SDX65, SM8450 and MSM8976, as well as RPMh clock support for
SDX65 and SM8450.

It cleans up the SMD RPM clock driver and it adds includes for
clk-provider.h throughout the clock providers that was lacking this.

* tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits)
  clk: qcom: turingcc-qcs404: explicitly include clk-provider.h
  clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h
  clk: qcom: mmcc-apq8084: explicitly include clk-provider.h
  clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h
  clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h
  clk: qcom: gcc-sm6350: explicitly include clk-provider.h
  clk: qcom: gcc-msm8994: explicitly include clk-provider.h
  clk: qcom: gcc-sm8350: explicitly include clk-provider.h
  clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver
  dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller
  clk: qcom: Add clock driver for SM8450
  clk: qcom: Add SDX65 GCC support
  clk: qcom: Add LUCID_EVO PLL type for SDX65
  dt-bindings: clock: Add SM8450 GCC clock bindings
  dt-bindings: clock: Add SDX65 GCC clock bindings
  clk: qcom: rpmh: add support for SM8450 rpmh clocks
  dt-bindings: clock: Add RPMHCC bindings for SM8450
  clk: qcom: smd-rpm: Drop binary value handling for buffered clock
  clk: qcom: smd-rpm: Drop the use of struct rpm_cc
  clk: qcom: smd-rpm: Drop MFD qcom-rpm reference
  ...
parents 9c337073 96ea2a42

Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for MSM8976



maintainers:

  - Stephen Boyd <sboyd@kernel.org>

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on MSM8976.



  See also:

  - dt-bindings/clock/qcom,gcc-msm8976.h



properties:

  compatible:

    enum:

      - qcom,gcc-msm8976

      - qcom,gcc-msm8976-v1.1



  clocks:

    items:

      - description: XO source

      - description: Always-on XO source

      - description: Pixel clock from DSI PHY0

      - description: Byte clock from DSI PHY0

      - description: Pixel clock from DSI PHY1

      - description: Byte clock from DSI PHY1



  clock-names:

    items:

      - const: xo

      - const: xo_a

      - const: dsi0pll

      - const: dsi0pllbyte

      - const: dsi1pll

      - const: dsi1pllbyte



  vdd_gfx-supply:

    description:

      Phandle to voltage regulator providing power to the GX domain.



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - vdd_gfx-supply

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    clock-controller@1800000 {

      compatible = "qcom,gcc-msm8976";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

      reg = <0x1800000 0x80000>;



      clocks = <&xo_board>,

               <&xo_board>,

               <&dsi0_phy 1>,

               <&dsi0_phy 0>,

               <&dsi1_phy 1>,

               <&dsi1_phy 0>;



      clock-names = "xo",

                    "xo_a",

                    "dsi0pll",

                    "dsi0pllbyte",

                    "dsi1pll",

                    "dsi1pllbyte";



      vdd_gfx-supply = <&pm8004_s5>;

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for SDX65



maintainers:

  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SDX65



  See also:

  - dt-bindings/clock/qcom,gcc-sdx65.h



properties:

  compatible:

    const: qcom,gcc-sdx65



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source

      - description: PCIE Pipe clock source

      - description: USB3 phy wrapper pipe clock source

      - description: PLL test clock source (Optional clock)

    minItems: 5



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk

      - const: pcie_pipe_clk

      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk

      - const: core_bi_pll_test_se # Optional clock

    minItems: 5



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sdx65";

      reg = <0x100000 0x1f7400>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,

               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",

                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for SM8450



maintainers:

  - Vinod Koul <vkoul@kernel.org>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SM8450



  See also:

  - dt-bindings/clock/qcom,gcc-sm8450.h



properties:

  compatible:

    const: qcom,gcc-sm8450



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: PCIE 0 Pipe clock source (Optional clock)

      - description: PCIE 1 Pipe clock source (Optional clock)

      - description: PCIE 1 Phy Auxillary clock source (Optional clock)

      - description: UFS Phy Rx symbol 0 clock source (Optional clock)

      - description: UFS Phy Rx symbol 1 clock source (Optional clock)

      - description: UFS Phy Tx symbol 0 clock source (Optional clock)

      - description: USB3 Phy wrapper pipe clock source (Optional clock)

    minItems: 2



  clock-names:

    items:

      - const: bi_tcxo

      - const: sleep_clk

      - const: pcie_0_pipe_clk # Optional clock

      - const: pcie_1_pipe_clk # Optional clock

      - const: pcie_1_phy_aux_clk # Optional clock

      - const: ufs_phy_rx_symbol_0_clk # Optional clock

      - const: ufs_phy_rx_symbol_1_clk # Optional clock

      - const: ufs_phy_tx_symbol_0_clk # Optional clock

      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock

    minItems: 2



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sm8450";

      reg = <0x00100000 0x001f4200>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;

      clock-names = "bi_tcxo", "sleep_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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@@ -22,10 +22,12 @@ properties: 
      - qcom,sc8180x-rpmh-clk

      - qcom,sdm845-rpmh-clk

      - qcom,sdx55-rpmh-clk

      - qcom,sdx65-rpmh-clk

      - qcom,sm6350-rpmh-clk

      - qcom,sm8150-rpmh-clk

      - qcom,sm8250-rpmh-clk

      - qcom,sm8350-rpmh-clk

      - qcom,sm8450-rpmh-clk



  clocks:

    maxItems: 1

MAINTAINERS

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@@ -15725,6 +15725,15 @@ F: Documentation/admin-guide/media/qcom_camss.rst 
F:	Documentation/devicetree/bindings/media/*camss*

F:	drivers/media/platform/qcom/camss/









QUALCOMM CLOCK DRIVERS









M:	Bjorn Andersson <bjorn.andersson@linaro.org>









L:	linux-arm-msm@vger.kernel.org









S:	Supported









T:	git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git









F:	Documentation/devicetree/bindings/clock/qcom,*









F:	drivers/clk/qcom/









F:	include/dt-bindings/clock/qcom,*

















QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER









M:	Niklas Cassel <nks@flawful.org>









L:	linux-pm@vger.kernel.org