perf/x86/intel/uncore: Add Sapphire Rapids server CHA support

mainline inclusion
from mainline-v5.15-rc1
commit 949b1138
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO



Intel-SIG: commit 949b1138 perf/x86/intel/uncore: Add Sapphire
Rapids server CHA support
This commit is backported for SPR PMU uncore support.

-------------------------------------

CHA merges the caching agent and Home Agent (HA) responsibilities of the
chip into a single block. It's one of the Sapphire Rapids server uncore
units.

The layout of the control registers for a CHA uncore unit is a little
bit different from the generic one. The CHA uncore unit also supports a
filter register for TID. So a specific format and ops are required.
Expose the common MSR ops which can be reused.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-3-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>