Commit e1fd35f5 authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Stephen Boyd
Browse files

clk: mediatek: use en_mask as a pure div_en_mask 



We no longer allow en_mask to be a combination of
pll_en_bit and div_en_mask, so remove pll_en_bit(bit0)
from en_mask to make en_mask a pure en_mask that only
used for pll dividers.

This commit continues the work done in commit 7cc4e1bb
("clk: mediatek: Fix asymmetrical PLL enable and disable
control") and commit f384c447 ("clk: mediatek:
Add configurable enable control to mtk_pll_data") to
clean up en_mask(bit0) default setting.

Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Signed-off-by: default avatarMandy Liu <mandyjh.liu@mediatek.com>
Link: https://lore.kernel.org/r/20220513073621.12923-1-mandyjh.liu@mediatek.com


Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 544e9ec7

drivers/clk/mediatek/clk-mt2701.c

+4 −4
Original line number Diff line number Diff line
@@ -935,13 +935,13 @@ static int mtk_pericfg_init(struct platform_device *pdev) 
	}



static const struct mtk_pll_data apmixed_plls[] = {

	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,

	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,

			PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,

		  HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),

	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,

	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,

		  HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),

	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,

	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,

				21, 0x230, 4, 0x0, 0x234, 0),

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,

				21, 0x240, 4, 0x0, 0x244, 0),

drivers/clk/mediatek/clk-mt2712.c

+15 −15
Original line number Diff line number Diff line
@@ -1223,38 +1223,38 @@ static const struct mtk_pll_div_table mmpll_div_table[] = { 
};



static const struct mtk_pll_data plls[] = {

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,

		HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),

	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,

	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,

		HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),

	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,

	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,

		0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),

	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,

	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,

		0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),

	PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,

	PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,

		0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),

	PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,

	PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,

		0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),

	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,

	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,

		0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),

	PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,

	PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,

		0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,

		0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),

	PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,

	PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,

		0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),

	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,

	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,

		0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),

	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,

	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,

		0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,

		mmpll_div_table),

	PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,

	PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,

		HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,

		armca35pll_div_table),

	PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,

	PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,

		0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,

		armca72pll_div_table),

	PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,

	PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,

		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),

};

drivers/clk/mediatek/clk-mt6765.c

+10 −10
Original line number Diff line number Diff line
@@ -748,26 +748,26 @@ static const struct mtk_gate apmixed_clks[] = { 
			_pcw_reg, _pcw_shift, NULL)	\



static const struct mtk_pll_data plls[] = {

	PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),

	PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0,

	    PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),

	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),

	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,

	    PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),

	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),

	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,

	    PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0,

	    (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,

	    0),

	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),

	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0,

	    0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),

	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),

	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0,

	    0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),

	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),

	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0,

	    HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,

	    0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),

	PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),

	PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0,

	    0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),

	PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),

	PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, 0,

	    PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),

};

drivers/clk/mediatek/clk-mt6779.c

+12 −12
Original line number Diff line number Diff line
@@ -1182,33 +1182,33 @@ static const struct mtk_gate apmixed_clks[] = { 
			_pcw_chg_reg, NULL)



static const struct mtk_pll_data plls[] = {

	PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),

	PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,

	    PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),

	PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),

	PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,

	    PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),

	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),

	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,

	    PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,

	    (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,

	    0x0234, 0, 0),

	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),

	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,

	    (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,

	    0, 0, 0, 0x0244, 0, 0),

	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),

	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,

	    0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,

	    0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),

	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),

	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,

	    0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),

	PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),

	PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,

	    (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,

	    0, 0, 0, 0x02b4, 0, 0),

	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),

	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,

	    (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,

	    0, 0, 0, 0x0284, 0, 0),

	PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),

	PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,

	    0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),

	PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),

	PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,

	    0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),

};

drivers/clk/mediatek/clk-mt6797.c

+10 −10
Original line number Diff line number Diff line
@@ -635,25 +635,25 @@ static int mtk_infrasys_init(struct platform_device *pdev) 
			NULL)



static const struct mtk_pll_data plls[] = {

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,

	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,

	    21, 0x220, 4, 0x0, 0x224, 0),

	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,

	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,

	    0x230, 4, 0x0, 0x234, 14),

	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,

	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,

	    0x244, 24, 0x0, 0x244, 0),

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,

	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,

	    0x250, 4, 0x0, 0x254, 0),

	PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,

	PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,

	    0x260, 4, 0x0, 0x264, 0),

	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,

	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,

	    0x270, 4, 0x0, 0x274, 0),

	PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,

	PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,

	    0x290, 4, 0x0, 0x294, 0),

	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,

	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,

	    0x2E4, 4, 0x0, 0x2E8, 0),

	PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,

	PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,

	    0x2A0, 4, 0x2A8, 0x2A4, 0),

	PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,

	PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000130, 0, 31,

	    0x2B4, 4, 0x2BC, 0x2B8, 0),

};