Commit f384c447 authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Stephen Boyd
Browse files

clk: mediatek: Add configurable enable control to mtk_pll_data 



In all MediaTek PLL design, bit0 of CON0 register is always
the enable bit.
However, there's a special case of usbpll on MT8192.
The enable bit of usbpll is moved to bit2 of other register.
Add configurable en_reg and pll_en_bit for enable control or
default 0 where pll data are static variables.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.

Reviewed-by: default avatarIkjoon Jang <ikjn@chromium.org>
Signed-off-by: default avatarWeiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-8-chun-jie.chen@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 7cc4e1bb

drivers/clk/mediatek/clk-mtk.h

+11 −9
Original line number Diff line number Diff line
@@ -213,13 +213,13 @@ struct mtk_pll_div_table { 
struct mtk_pll_data {

	int id;

	const char *name;

	uint32_t reg;

	uint32_t pwr_reg;

	uint32_t en_mask;

	uint32_t pd_reg;

	uint32_t tuner_reg;

	uint32_t tuner_en_reg;

	uint8_t tuner_en_bit;

	u32 reg;

	u32 pwr_reg;

	u32 en_mask;

	u32 pd_reg;

	u32 tuner_reg;

	u32 tuner_en_reg;

	u8 tuner_en_bit;

	int pd_shift;

	unsigned int flags;

	const struct clk_ops *ops;
@@ -228,11 +228,13 @@ struct mtk_pll_data { 
	unsigned long fmax;

	int pcwbits;

	int pcwibits;

	uint32_t pcw_reg;

	u32 pcw_reg;

	int pcw_shift;

	uint32_t pcw_chg_reg;

	u32 pcw_chg_reg;

	const struct mtk_pll_div_table *div_table;

	const char *parent_name;

	u32 en_reg;

	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */

};



void mtk_clk_register_plls(struct device_node *node,

drivers/clk/mediatek/clk-pll.c

+10 −5
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ struct mtk_clk_pll { 
	void __iomem	*tuner_en_addr;

	void __iomem	*pcw_addr;

	void __iomem	*pcw_chg_addr;

	void __iomem	*en_addr;

	const struct mtk_pll_data *data;

};
@@ -56,7 +57,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw) 
{

	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);



	return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;

	return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;

}



static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
@@ -248,8 +249,8 @@ static int mtk_pll_prepare(struct clk_hw *hw) 
	writel(r, pll->pwr_addr);

	udelay(1);



	r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;

	writel(r, pll->base_addr + REG_CON0);

	r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);

	writel(r, pll->en_addr);



	div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;

	if (div_en_mask) {
@@ -290,8 +291,8 @@ static void mtk_pll_unprepare(struct clk_hw *hw) 
		writel(r, pll->base_addr + REG_CON0);

	}



	r = readl(pll->base_addr + REG_CON0) & ~CON0_BASE_EN;

	writel(r, pll->base_addr + REG_CON0);

	r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);

	writel(r, pll->en_addr);



	r = readl(pll->pwr_addr) | CON0_ISO_EN;

	writel(r, pll->pwr_addr);
@@ -333,6 +334,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, 
		pll->tuner_addr = base + data->tuner_reg;

	if (data->tuner_en_reg)

		pll->tuner_en_addr = base + data->tuner_en_reg;

	if (data->en_reg)

		pll->en_addr = base + data->en_reg;

	else

		pll->en_addr = pll->base_addr + REG_CON0;

	pll->hw.init = &init;

	pll->data = data;