Commit 7cc4e1bb authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Stephen Boyd
Browse files

clk: mediatek: Fix asymmetrical PLL enable and disable control 



In fact, the en_mask is a combination of divider enable mask
and pll enable bit(bit0).
Before this patch, we enabled both divider mask and bit0 in prepare(),
but only cleared the bit0 in unprepare().
In the future, we hope en_mask will only be used as divider enable mask.
The enable register(CON0) will be set in 2 steps:
first is divider mask, and then bit0 during prepare(), and vice versa.
But considering backward compatibility, at this stage we allow en_mask
to be a combination or a pure divider enable mask.
And then we will make en_mask a pure divider enable mask in another
following patch series.

Reviewed-by: default avatarIkjoon Jang <ikjn@chromium.org>
Signed-off-by: default avatarWeiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-7-chun-jie.chen@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 197ee543

drivers/clk/mediatek/clk-pll.c

+16 −4
Original line number Diff line number Diff line
@@ -238,6 +238,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) 
{

	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);

	u32 r;

	u32 div_en_mask;



	r = readl(pll->pwr_addr) | CON0_PWR_ON;

	writel(r, pll->pwr_addr);
@@ -247,9 +248,14 @@ static int mtk_pll_prepare(struct clk_hw *hw) 
	writel(r, pll->pwr_addr);

	udelay(1);



	r = readl(pll->base_addr + REG_CON0);

	r |= pll->data->en_mask;

	r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;

	writel(r, pll->base_addr + REG_CON0);



	div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;

	if (div_en_mask) {

		r = readl(pll->base_addr + REG_CON0) | div_en_mask;

		writel(r, pll->base_addr + REG_CON0);

	}



	__mtk_pll_tuner_enable(pll);
@@ -268,6 +274,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) 
{

	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);

	u32 r;

	u32 div_en_mask;



	if (pll->data->flags & HAVE_RST_BAR) {

		r = readl(pll->base_addr + REG_CON0);
@@ -277,8 +284,13 @@ static void mtk_pll_unprepare(struct clk_hw *hw) 


	__mtk_pll_tuner_disable(pll);



	r = readl(pll->base_addr + REG_CON0);

	r &= ~CON0_BASE_EN;

	div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;

	if (div_en_mask) {

		r = readl(pll->base_addr + REG_CON0) & ~div_en_mask;

		writel(r, pll->base_addr + REG_CON0);

	}



	r = readl(pll->base_addr + REG_CON0) & ~CON0_BASE_EN;

	writel(r, pll->base_addr + REG_CON0);



	r = readl(pll->pwr_addr) | CON0_ISO_EN;